scholarly journals The limits of semiconductor technology and oncoming challenges in computer micro architectures and architectures

2004 ◽  
Vol 17 (3) ◽  
pp. 285-312
Author(s):  
Mile Stojcev ◽  
Teufik Tokic ◽  
Ivan Milentijevic
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
New Technology ◽  
Process Technology ◽  
History Of ◽  
And Performance ◽  
Thread Level Speculation ◽  
Exponential Rates ◽  
Architecture And Design ◽  
Integrated Circuit Industry

In the last three decades the world of computers and especially that of microprocessors has been advanced at exponential rates in both productivity and performance. The integrated circuit industry has followed a steady path of constantly shrinking devices geometries and increased functionality that larger chips provide. The technology that enabled this exponential growth is a combination of advancements in process technology, micro architecture architecture and design and development tools. Together, these performances and functionality improvements have resulted in a history of new technology generations every two to three years, commonly referred to as-Moore Law. Each new generation has approximately doubled logic circuit density and increased performance by about 40%. This paper overviews some of the micro architectural techniques that are typical for contemporary high-performance microprocessors. The techniques are classified into those that increase the concurrency in instruction processing, while maintaining the appearance of sequential processing (pipelining, super-scalar execution out-of-order execution, etc), and those that exploit program behavior (memories hierarchies, branch predictors, trace caches, etc). In addition the paper also discusses micro architectural techniques likely to be used in the near future such as micro architectures with multiple sequencers and thread-level speculation, and micro architectural techniques intended for minimization of power consumption.

scholarly journals Giga-Scale Integration System-On-A-Chip Design: Challenges and Noteworthy Solutions

2020 ◽  
Vol 8 (6) ◽  
pp. 741-746
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Chip Design ◽  
Future Challenges ◽  
System On A Chip ◽  
And Performance ◽  
Exponential Rates ◽  
Scale Integration ◽  
Bus Architecture ◽  
Circuit Technology

In all respects of the last five decades, integrated circuit technology has advanced at exponential rates in both productivity and performance. Giga-Scale Integration (GSI) System-On-A-Chip (SoC) designs have become one of the main drivers of the integrated circuit technology in recent years. The objective of this work is to understand the challenges of Giga-scale SoC integration in nanometer technologies, and identify promising conveniences for innovation. Physical designs are crucial for SoC integration and in our work we identify them with details. In future the couplings and interactions among system components will increase as we put more of the system on a silicon die. Therefore the system designers will face challenges in several areas and we describe these future challenges briefly. Developing a design driver for GSI SoC design is important. With the help of this design driver we provide the design methodology, which ensures the high performance of the design. We present two noteworthy solutions which overcome the challenges of GSI SoC design. One is reuse and integration and another is efficient bus architecture. We also provide the challenges for verification of GSI SoC and methods to overcome these challenges.

scholarly journals Self-healing Concrete and Environmental Health

2018 ◽  
Vol 5 (3) ◽  
pp. 107-112 ◽  
Author(s):  
Mehrdad Amiri ◽  
Javad Majrouhi Sardroud ◽  
Ali Golsoorat Pahlaviani
Keyword(s):  
Construction Industry ◽  
High Performance ◽  
New Technologies ◽  
New Technology ◽  
Steel Corrosion ◽  
Self Healing ◽  
Natural Processes ◽  
The World ◽  
And Performance ◽  
Creativity And Innovation

Nanotechnology will serve as a suitable solution to achieve high performance in future construction. Using this new technology results in creativity and innovation in the construction industry. One of these new technologies is the smart concrete which has received much emphasis in recent years. Many research and experiments have been conducted in scientific research centers around the world in this regard. It is an undeniable fact that concrete structures are prone to cracking. Natural processes have caused cracks in the concrete through which harmful substances entered the concrete leading to steel corrosion. To tackle this issue through the conventional method of concrete restorative, materials, especially polymers which are also harmful to the environment, are used. An alternative that the scientists have achieved is to employ bacteria in concrete through which to produce self-healing concrete and also to reduce the problems regarding the maintenance of concrete for the environment. Bacteria contribute to the durability and performance of the concrete and increase the service life of the concrete.

scholarly journals PERFORMANCE CHARACTERISTICS of Eugene Goossens’s Concerto for Oboe and Orchestra

2021 ◽  
Vol 60 (60) ◽  
pp. 167-183
Author(s):  
Jin Tao
Keyword(s):  
Performance Analysis ◽  
20Th Century ◽  
Research Methodology ◽  
High Performance ◽  
Scientific Activity ◽  
Performance Characteristics ◽  
Early 20Th Century ◽  
Performance Skills ◽  
History Of ◽  
And Performance

Statement of the problem. The study of the process of development of the concert style of oboe performance is a relevant area of modern musicology, as evidenced, in particular, by the scientific activity of the International Double Reed Society (IDRS) and works of other researchers on the history of the instrument and its repertoire starting with the second half of the 20 century (Bate, 1975; Bartalozzi, 1967; Reeves & Hooper, 1985; Goossens & Roxburgh, 2001). The concept of “concert oboe” is actualized by V. Martynova (2018, 2019) on the basis of the performance art of the 19th – 20th centuries. As for works for oboe of the early 20th century, in particular by E. Goossens, there are a few studies devoted to the development of modern style of the concert oboe (Del Mar, 1984; Lopez-Pelaez-Casellas & Garcia-Herrera, 2019) and to E. Goossens’s Concerto (Woodworth, 2016). This determines the scientific novelty of this research, which involves genre-style and performance analysis of the Concerto. The purpose of this study is to identify typical genre-stylistic and performance characteristics of E. Goossens’s composition in the context of the development of the concert style of oboe performance. The research methodology is based, first, on the genre and style approach, which is traditional for musicology, in particular, on research on the code of reflexivity (Shapovalova, 2006), and pastoral genre in music (Shapovalova, Chernyavska, Govorukhina & Nikolaievska, 2021). Another methodological dimension is related to the positions of analytical interpretology and principles of performance analysis (Nikolaievska, 2020), which focus on such elements as form-creation, performance dramaturgy, performance poetics. Results and conclusions. The typical genre and stylistic features of E. Goossens’composition refer to the traditions of the romantic concerto (onemovement structure; the presence of a symphonic model of the genre; the use of initial intonation as the main sound symbol of the work; the absence of a single tonal centre; reflexivity; the involvement of pastoral colour as an established image of the instrument). From the viewpoint of performance poetics we have marked the overcoming of the formality of rondeau nature by the continuity of performance form-creation; the presence of such difficulties requiring high performance skills of an oboist as playing of whole-tone scale, high notes and extreme sounds of the registers, polyrhythmic structures, the abundance of virtuoso passages in the composition, the variety of articulation techniques, fast-frequency vibrato, etc., which is crucial in the process of development of the concert style of oboe performance in the early 20th century.

Process Design & Integration of Salicide and Source/Drain Process Modules for Improved Device Performance

1998 ◽  
Vol 525 ◽  
Author(s):  
Pushkar P. Apte ◽  
Sharad Saxena ◽  
Suraj Rao ◽  
Karthik Vasanth ◽  
Douglas A. Prinslow ◽  
...  
Keyword(s):  
Process Design ◽  
Integrated Circuit ◽  
High Performance ◽  
Performance Enhancement ◽  
Process Integration ◽  
Channel Length ◽  
Trade Offs ◽  
Design Integration ◽  
And Performance ◽  
Circuit Delays

ABSTRACTIn integrated circuit (IC) fabrication, understanding and optimizing process interactions and variability is critical for swift process integration and performance enhancement, especially at dimensions ≤0.25μm. We present here an approach to address this challenge, and we apply it to improve the process design for two critical modules in a typical CMOS IC process—salicide and source/drain. Together, these modules impact the silicide-to-diffusion contact resistance (Rc), and the gate sheet resistance (Rs); which, in turn, significantly affect transistor series resistance and circuit delays respectively. In our approach, we have investigated a process domain consisting of both silicide and source/drain process variables; and we have developed a quantitative framework for analysis and optimization, along with qualitative insight into underlying the physical mechanisms. We demonstrate that the transistor drive current (Id) improves by ≈5‥, and circuit performance, as measured by the figure-of-merit (FOM), by ≈4‥. This improvement is significant, and an added benefit is that other transistor characteristics such as effective channel length, off-current, substrate current etc. are affected minimally. Finally, we use this approach to optimize trade-offs such as Rc vs Rs and performance vs manufacturability; thus enabling manufacturable processes that meet the requirements for high performance.

scholarly journals High Speed Back-Bias Voltage (VBB) Generator with Improved Pumping Current

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1835 ◽  
Author(s):  
Taegun Yim ◽  
Choongkeun Lee ◽  
Hongil Yoon
Keyword(s):  
Metal Oxide ◽  
Bias Voltage ◽  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Negative Voltage

Due to the advance of dynamic random access memory (DRAM) technologies with the steadfast increase of density with aggressively scaled storage capacitors, the supply voltage has been lowered to under 1 V to reduce power consumption. The above progress has been accompanied by the increasingly difficult task of sensing cell data reliably. One of the essential methods to preserve sustainable data retention characteristic is to curtail the sub-threshold leakage current by using a negative voltage bias for the bulk of access transistors. This negative back-bias is generated by a back-bias voltage generator. This paper proposes a novel high-speed back-bias voltage (VBB) generator with a cross-coupled hybrid pumping scheme. The conventional circuit uses one fixed voltage to control the gates of discharge of the p-channel metal oxide semiconductor (PMOS) and transfer n-channel metal oxide semiconductor (NMOS), respectively. However, the proposed circuit adds an auxiliary pump, thereby able to control more aptly with a lower negative voltage when discharging and a higher positive voltage when transferring. As a result, the proposed circuit achieves a faster pump-down speed and higher pumping current at a lower supply voltage compared to conventional circuits. The H-simulation program with integrated circuit emphasis (HSPICE) simulation results with the Taiwan semiconductor manufacturing company (TSMC) 0.18 um process technology indicates that the proposed circuit has about a 20% faster pump-down speed at a supply voltage of voltage common collector (VCC) = 1.2 V and about 3% higher pumping current at VBB from −0.6 V to −1 V with the ability to generate a near 3% higher ratio of |VBB|/VCC at VCC = 0.6 V compared to conventional circuits. Hence, the proposed circuit is extremely suitable and promising for future low-power and high-performance DRAM applications.

ARM Dual Core Product Demonstration with 2.5D Through-Silicon-Via (TSV)

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000665-000693
Author(s):  
Michael Kelly ◽  
Rick Reed
Keyword(s):  
High Speed ◽  
High Performance ◽  
Functional System ◽  
Process Technology ◽  
Test Vehicle ◽  
Through Silicon Via ◽  
The Real Estate ◽  
Key Factor ◽  
And Performance ◽  
Dual Core

Through-silicon-via (TSV) package construction offers several silicon integration advantages that are being validated by leading technology providers. This paper will describe a System in Package (SiP) design utilizing two functional system-on-chip (SoC) ARM dual-core Cortex-A9 processors connected across a 2.5D silicon interposer. The test vehicle was designed to demonstrate high speed and high bandwidth communication between multiple chips. The two logic chips were designed by Open Silicon, Inc. and fabricated by GLOBALFOUNDRIES on their 28nm-SLP (Super Low Power) process technology. GLOBALFOUNDRIES also fabricated the 2.5D interposer using their 65nm manufacturing flow. Amkor Technology provided the final assembly utilizing advanced TSV packaging technologies such as copper pillar bumping and mass reflow bonding. This is a pivotal demonstration of the heterogeneous die integration approach. A silicon process node or package interconnect density can either preserve or limit inter-chip communication when comparing SoC versus SiP approaches. Connecting two dual-core Cortex-A9 processors within a single package illustrated the expansion of function through multiple die. The test vehicle also implies that a large IC can be re-architected into smaller constituents to increase yield or design flexibility. By utilizing the best technology node for price and performance, 2.5D packaging can lower overall system cost of ownership or conversely, can expand overall performance through multiple high performance ICs. Chip designers are facing increased complexity and higher costs in order to move to smaller IC geometries and the adoption of 2.5D TSV technology will increase the options of construction (one vs. multiple die/SoCs). Having the flexibility to design with one or multiple die while maintaining high performance levels can offset the real estate costs of advanced nodes, permit silicon die reuse, improve yield and decrease overall product risk. The designer must choose the most appropriate silicon and assembly processes that satisfy the needs of each of the major functions in the overall system. Amkor's assembly process for this key product construction has been demonstrated on a range of products for the communications, graphics and the mobile markets. Process flexibility has been a key factor in addressing different markets and package complexity.

scholarly journals An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing

2012 ◽  
Vol 2012 ◽  
pp. 1-15 ◽  
Author(s):  
Andrew G. Schmidt ◽  
William V. Kritikos ◽  
Shanyuan Gao ◽  
Ron Sass
Keyword(s):  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
Large Scale ◽  
The Body ◽  
And Performance ◽  
On Chip ◽  
Point To Point ◽  
Computing Machines ◽  
Performance Computing

As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the high-performance computing community which needs to assemble many of these devices into very large scale, parallel computing machines. This paper describes an integrated on-chip/off-chip network that has been implemented on an all-FPGA computing cluster. The system supports MPI-style point-to-point messages, collectives, and other novel communication. Results include the resource utilization and performance (in latency and bandwidth).

New Technology to Recycle and Rebuild Worn Polyurethane Pipeline Pigs

2000 ◽  
Author(s):  
Graham D. Bruce
Keyword(s):  
High Performance ◽  
Mechanical Characteristics ◽  
New Technology ◽  
Cost Savings ◽  
Process Technology ◽  
Significant Cost ◽  
Oil Pipeline ◽  
Successful Program ◽  
Thermoset Polymer

SUNcast Polyurethanes Inc. has developed a proprietary process technology that makes it possible to rebuild worn Polyurethane (PU) discs, cups and solid cast pipeline pigs. The technology creates a completely secure bond between the virgin and cured cast elastomer PU enabling rebuilt parts to perform “as new”. This paper addresses the mechanical characteristics of the bond possible with this technology and offers the results of a case study on a successful program to rebuild over fifty 24″ solid cast pigs for a crude oil pipeline. Cast elastomer PU is an expensive thermoset polymer which has not been readily recyclable. SUNcast’s technology offers pipeline operators, contractors and inspection companies an opportunity to recycle what is now waste back into high performance pigging products at significant cost savings.

Characterization of RF Sputtered ZnO Piezoelectric Films Using Transmission Electron Microscope

1975 ◽  
Vol 33 ◽  
pp. 86-87
Author(s):  
Kemining W. Yeh ◽  
Richard S. Muller ◽  
Wei-Kuo Wu ◽  
Jack Washburn
Keyword(s):  
Integrated Circuit ◽  
Acoustic Waves ◽  
New Technology ◽  
Surface Acoustic Waves ◽  
Electromechanical Properties ◽  
Leading Role ◽  
Saw Devices ◽  
Transmission Electron ◽  
High Degree

Considerable and continuing interest has been shown in the thin film transducer fabrication for surface acoustic waves (SAW) in the past few years. Due to the high degree of miniaturization, compatibility with silicon integrated circuit technology, simplicity and ease of design, this new technology has played an important role in the design of new devices for communications and signal processing. Among the commonly used piezoelectric thin films, ZnO generally yields superior electromechanical properties and is expected to play a leading role in the development of SAW devices.

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