Shape Measurement of Solder Bumps by Shape-from-Focus Using Varifocal Mirror

2006 ◽  
Vol 18 (6) ◽  
pp. 722-727
Author(s):  
Jun Mitsudo ◽  
◽  
Akira Ishii
Keyword(s):  
Copper Alloy ◽  
Solder Bump ◽  
Optical Axis ◽  
Focal Point ◽  
Shape Measurement ◽  
Depth Range ◽  
Focal Points ◽  
Depth Data ◽  
Solder Bumps ◽  
Shape From Focus

We measured solder bumps on an LSI package board presented for inspection based on the shape from focus. We used a copper-alloy mirror deformed by a piezoelectric actuator as a varifocal mirror to build a motionless yet fast focusing mechanism. The varifocal mirror was at the image focal point of the image-taking lens so that lateral magnification was constant during focusing and orthographic projection was established. A focused plane was shifted along the optical axis with a precision of 1.4μm in a depth range of 1.5mm by driving the varifocal mirror. A magnification of 1.97 was maintained during focusing. Evaluating the curvature of field and removing its effect from the depth data reduced errors. The shape of 208 solder bumps 260-μm high spaced 500μm on the board was measured. The 10mm×10mm board was segmented into partly overlapping 3×4 sections. We captured 101 images in each section with a high-resolution camera at different focal points at 15-μm intervals. The shape of almost the entire upper-hemisphere of a solder bump could be measured. Error in measuring bump heights was less than 12μm.

Electrolytic Deposition of Fine Pitch Sn/Cu Solder Bumps for Flip Chip Packaging

2012 ◽  
Vol 2012 (1) ◽  
pp. 000729-000734
Author(s):  
Stephen Kenny ◽  
Kai Matejat ◽  
Sven Lamprecht ◽  
Olivier Mann
Keyword(s):  
Copper Alloy ◽  
Flip Chip ◽  
Solder Bump ◽  
Electroless Nickel ◽  
Practical Experience ◽  
Electrolytic Deposition ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Solder Bumps

Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate alloy solder paste. The continuing trend towards increased miniaturization and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 150μm for these applications. This paper describes latest developments in the electrolytic deposition of solder to replace the stencil printing process; results from production of 90μm bump pitch solder arrays with tin/copper alloy are given. The solder bump is produced with a specially developed electrolytic tin process which fills a photo resist defined structure on the SRO. The photoresist dimensions determine the volume of solder produced and the subsequent bump height after reflow. Investigations on the bump reliability after reflow are shown including copper alloy concentration at 0.7% and x-ray investigation to confirm uniform metal deposition. The self centering mechanism found in the bump production process during reflow is presented and the capability to correct photoresist registration issues. The solder bumps are shown as deposited onto an electroless nickel/gold or electroless nickel/palladium/gold final finish which serves also as a barrier layer to copper diffusion into the solder bump. Discussion of further development work in the production of alloys of tin/copper together with silver are given with first test results.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

ON OPTIMUM PUPIL FIELDS WITH MAXIMUM ELECTRIC FIELD COMPONENT IN FOCUS

2010 ◽  
Vol 19 (01) ◽  
pp. 189-201
Author(s):  
H. P. URBACH ◽  
S. F. PEREIRA ◽  
D. J. BROER
Keyword(s):  
Electric Field ◽  
Field Component ◽  
Optical Axis ◽  
Focal Point ◽  
Longitudinal Component ◽  
Electric Field Component ◽  
Incident Power ◽  
Entrance Pupil ◽  
Maximum Electric Field ◽  
High Na Lens

The field in the entrance pupil of a high NA lens can be optimized such that, for given incident power, the electric field component in a given direction in the focal point is maximum. If the field component is chosen parallel to the optical axis, the longitudinal component is maximized and it is found that the optimum longitudinal component is narrower than the Airy spot. We discuss how this can be used to obtain higher resolution in photolithography when a resist is used that is sensitive to only the longitudinal component. We describe a proposition for realizing such resist.

Quantitative Evaluation of Voids in Lead Free Solder Joints

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi
Keyword(s):  
Solder Bump ◽  
Solder Joints ◽  
Void Formation ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
X Ray ◽  
Size And Shape ◽  
Solder Bumps ◽  
Free Solder

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Diagram of Electromigration Pattern in Eutectic Pb-Sn and Pb-Free Solders

2005 ◽  
Vol 297-300 ◽  
pp. 837-843
Author(s):  
Takashi Hasegawa ◽  
Masumi Saka
Keyword(s):  
Current Density ◽  
Solder Bump ◽  
High Density ◽  
Solder Bumps ◽  
Multi Phase ◽  
High Density Packaging

Solder is the most frequently used alloy, which serves as the bonding metal for electronics components. Recently, the interconnected bump is distinctly downsizing its bulk along with the integration of high-density packaging. The evaluation of electromigration damage for solder bumps is indispensable. Hence, it is fairly urgent to understand the mechanism of the electromigration damage to be capable of securing reliability of the solder bump and ultimately predicting its failure lifetime. Electromigration pattern in multi-phase material is determined by the combination of current density, temperature and current-applying time. In this paper, diagram of electromigration pattern (DEP) in solders is presented, where both of eutectic Pb-Sn and Pb-free solders are treated. DEP gives the basis for discussing and predicting the electromigration damage in solders.

KNOT POINTS IN TWO-DIMENSIONAL MAPS AND RELATED PROPERTIES

2009 ◽  
Vol 19 (02) ◽  
pp. 545-555 ◽  
Author(s):  
F. TRAMONTANA ◽  
L. GARDINI ◽  
D. FOURNIER-PRUNARET ◽  
P. CHARGE
Keyword(s):  
Focal Point ◽  
Singular Line ◽  
Two Dimensional ◽  
Focal Points ◽  
Singular Set ◽  
One Dimensional ◽  
Attracting Set ◽  
Straight Line ◽  
Special Character ◽  
Stable And Unstable Sets

We consider the class of two-dimensional maps of the plane for which there exists a whole one-dimensional singular set (for example, a straight line) that is mapped into one point, called a "knot point" of the map. The special character of this kind of point has been already observed in maps of this class with at least one of the inverses having a vanishing denominator. In that framework, a knot is the so-called focal point of the inverse map (it is the same point). In this paper, we show that knots may also exist in other families of maps, not related to an inverse having values going to infinity. Some particular properties related to focal points persist, such as the existence of a "point to slope" correspondence between the points of the singular line and the slopes in the knot, lobes issuing from the knot point and loops in infinitely many points of an attracting set or in invariant stable and unstable sets.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Detection of Solder Bump Defects in Electronic Packages Using Local Temporal Coherence Analysis of Laser Ultrasonic Signals

2009 ◽  
Vol 131 (1) ◽  
Author(s):  
Jin Yang ◽  
I. Charles Ume
Keyword(s):  
Solder Bump ◽  
Temporal Coherence ◽  
Acoustic Microscopy ◽  
Inspection System ◽  
Laser Ultrasound ◽  
Electronic Packages ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Inspection

Microelectronics packaging technology has evolved from through-hole and bulk configurations to surface-mount and small-profile configurations. Surface mount devices, such as flip chip packages, chip scale packages, and ball grid arrays, use solder bump interconnections between them and substrates/printed wiring boards. Solder bumps, which are hidden between the device and the substrate/board, are difficult to inspect. A solder bump inspection system was developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder joint/bump defects, including missing, misaligned, open, and cracked solder joints/bumps in flip chips, chip scale packages, and multilayer ceramic capacitors. This system uses a pulsed Nd:YAG laser to induce ultrasound in the electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement response on the package surface using the interferometric technique. This paper presents a local temporal coherence (LTC) analysis of laser ultrasound signals and compares it to previous signal-processing methods, including error ratio and correlation coefficient methods. The results showed that LTC analysis increased measurement accuracy and sensitivity for inspecting solder bump defects in electronic packages. Laser ultrasound inspection results are also compared with X-ray and C-mode scanning acoustic microscopy results. In particular, this paper discusses defect detection for 6.35×6.35×0.6 mm3 flip chips and flip chips (“SiMAF;” Siemens AG) with lead-free solder bumps.

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