scholarly journals Analytical Modeling of Line-Tunneling TFETs Based on Low-Bandgap Semiconductors

2021 ◽  
Vol 23 (3) ◽  
pp. 247-253
Author(s):  
Bahareh Safari ◽  
Seyed Ebrahim Hosseini
Keyword(s):  
Analytical Modeling ◽  
Doping Concentration ◽  
Current Model ◽  
Complex Form ◽  
Drain Current ◽  
Gate Insulator ◽  
Low Bandgap ◽  
Effective Factor ◽  
Bandgap Semiconductors ◽  
Current Equation

The combination of two techniques: low-bandgap semiconductor and line-tunneling structure is an effective way to achieve the highest on-current in TFETs. In this paper, design of low-bandgap line-tunneling TEFT and its analytical modeling of drain current equation is proposed. The previously suggested drain current equation for the low-bandgap line-tunneling TEFT has been explained in a relatively complex form based on the minimum tunnel path that is an effective factor in determining band-to-band tunneling (BTBT). It has been simplified in this paper and reformulated based on gate-to-source voltage. Important design factors such as source doping concentration, material and thickness of the gate-insulator were examined by simulation and numerical calculations based on the minimum tunnel path for two low-bandgap In0.88Ga0.12As and relatively high-bandgap GaSb semiconductors. The comparison of the results obtained from simulations with the proposed analytical drain current model show a good agreement. Drain doping concentration, is an effective factor on the off-state current of low-bandgap TFET. This factor was examined in order to reduce the off-current.

An Accurate Drain Current Model for Symmetric Dual Gate Tunnel FET Using Effective Tunneling Length

2018 ◽  
Vol 9 (1) ◽  
pp. 85-91 ◽  
Author(s):  
Sasmita Sahoo ◽  
Sidhartha Dash ◽  
Guru P. Mishra
Keyword(s):  
Performance Indicators ◽  
Analytical Modeling ◽  
Present Model ◽  
Current Model ◽  
Practical Importance ◽  
Drain Current ◽  
Subthreshold Slope ◽  
Tunnel Fet ◽  
Dual Gate ◽  
Tcad Sentaurus

Introduction: Here we propose an accurate drain current model for a Symmetric Dual Gate Tunnel FET (SDG-TFET) using effective tunneling length and generation rate of carrier over tunneling junction area. Analytical Modeling: The surface potential of the model is obtained by solving 2-dimensional Poisson’s equation and further extends to determine the magnitude of initial tunneling length and final tunneling length. The different DC performance indicators like drain current (ID), threshold voltage (Vth), transconductance (gm) and Subthreshold Slope (SS) for the present model are extensively investigated and the results are compared with that of Single Gate Tunnel FET (SGTFET). Conclusion: The practical importance of this model relies on its accuracy and improved electrostatic performance over SG-TFET. The analytical model results are validated using TCAD Sentaurus (Synopsys) device simulator.

Modeling and Simulation of Nanoscale Lateral Gaussian Doped Channel Asymmetric Double Gate MOSFET

2015 ◽  
Vol 36 ◽  
pp. 51-63 ◽  
Author(s):  
Vandana Kumari ◽  
Manoj Saxena ◽  
Mridula Gupta
Keyword(s):  
Analytical Modeling ◽  
Current Model ◽  
Drain Current ◽  
Doping Profile ◽  
Mode Analysis ◽  
Double Gate ◽  
Digital Performance ◽  
Dg Mosfet ◽  
Double Gate Mosfet ◽  
The Impact

This work presents the drain current model using Evanescent Mode Analysis (EMA) for nanoscale Double Gate MOSFET having Gaussian doping profile along the horizontal direction in the channel i.e. from source to drain region. Due to heavily doped channel, band gap narrowing effect is incorporated in the analytical modeling scheme. The various parameters evaluated in this work using analytical modeling scheme are surface potential, electric field, threshold voltage, sub-threshold slope and drain current. The impact of peak Gaussian doping profile on the drain current and trans-conductance has been demonstrated which are important for assessing the analog performance of the device. The results are also compared with the uniformly doped DG MOSFET. The asymmetric behaviour of Gaussian doped DG MOSFET has also been investigated. In addition to this, digital performance of Gaussian doped DG MOSFET has also been assessed using exhaustive device simulation.

Suppression of Hole Current in Graphene Transistors with N-Type Doped SiC Source/Drain Regions

2012 ◽  
Vol 717-720 ◽  
pp. 679-682 ◽  
Author(s):  
Yuichi Nagahisa ◽  
Eisuke Tokumitsu
Keyword(s):  
Graphene Layer ◽  
Doping Concentration ◽  
Drain Current ◽  
The Other ◽  
Gate Insulator ◽  
High Temperature Annealing ◽  
Current Ratio ◽  
Ambipolar Behavior ◽  
Heavily Doped ◽  
Hole Current

To achieve graphene channel transistors which have high on/off drain current ratio and unipolar behavior of drain current – gate voltage (ID-VG) characteristics, we fabricated and characterized the top gated graphene channel transistors with n-type doped SiC source/drain regions. Graphene layer was formed on SiC by high temperature annealing in vacuum, and Al2O3 was used as a gate insulator. For the graphene channel transistor with heavily doped n-SiC source/drain regions (doping concentration ND=4.5x1019cm-3) and a 4~6ML graphene channel, ambipolar behavior was observed. On the other hand, when ND was reduced to 4.5x1018cm-3 and a thin graphene layer was used, the suppression of hole current in ID-VG curve was observed.

An Analytical Drain Current Model for Dual-material Gate Graded - channel and Dual-oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET

2019 ◽  
Vol 9 (2) ◽  
pp. 291-297
Author(s):  
Hind Jaafar ◽  
Abdellah Aouaj ◽  
Ahmed Bouziane ◽  
Benjamin Iñiguez
Keyword(s):  
Current Model ◽  
Drain Current ◽  
Oxide Thickness ◽  
Subthreshold Current ◽  
The Poisson Equation ◽  
Strong Inversion ◽  
Cylindrical Form ◽  
Silvaco Atlas ◽  
Dual Material ◽  
Good Agreement

Background: A novel Dual Material Gate Graded Channel and Dual Oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET is presented in this paper. Methods: Analytical model of drain current is developed using a quasi-two-dimensional cylindrical form of the Poisson equation and is expressed as a function of the surface potential, which is calculated using the expressions of the current density. Results: Comparison of the analytical results with 3D numerical simulations using Silvaco Atlas - TCAD software presents a good agreement from subthreshold to strong inversion regime and for different bias voltages. Conclusion: Two oxide thicknesses with different permittivity can effectively improve the subthreshold current of DMG-GC-DOT MOSFET.

Wide range modulation of synaptic weight in thin-film transistors with hafnium oxide gate insulator and indium-zinc oxide channel layer for artificial synapse application

Nanoscale ◽  
2021 ◽  
Author(s):  
Keonwon Beom ◽  
Jimin Han ◽  
Hyun-Mi Kim ◽  
Tae-Sik Yoon
Keyword(s):  
Thin Film ◽  
Zinc Oxide ◽  
Thin Film Transistors ◽  
Hafnium Oxide ◽  
Synaptic Weight ◽  
Drain Current ◽  
Gate Insulator ◽  
Channel Layer ◽  
Indium Zinc Oxide ◽  
Wide Range

Wide range synaptic weight modulation with a tunable drain current was demonstrated in thin-film transistors (TFTs) with a hafnium oxide (HfO2−x) gate insulator and an indium-zinc oxide (IZO) channel layer...

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