scholarly journals Low Power Double Gate Fin FET Based Sense Amplifier

IJARCCE ◽  
2015 ◽  
pp. 252-258
Author(s):  
Pallavi Priyadarshni ◽  
S.N. Singh
Keyword(s):  
Low Power ◽  
Double Gate ◽  
Sense Amplifier

scholarly journals Design and Analysis of Low Power Latch Sense Amplifier

2014 ◽  
Vol 9 (6) ◽  
pp. 69-73 ◽  
Author(s):  
Kamal Pandey ◽  
◽  
Vishal Yadav
Keyword(s):  
Low Power ◽  
Sense Amplifier

32 nm high current performance double gate MOSFET for low power CMOS circuits

2014 ◽  
Vol 102 (3) ◽  
pp. 347-361
Author(s):  
Morteza Rahimian ◽  
Ali A. Orouji ◽  
Amirhossein Aminbeidokhti
Keyword(s):  
Low Power ◽  
Cmos Circuits ◽  
Double Gate ◽  
High Current ◽  
Double Gate Mosfet ◽  
Low Power Cmos

Ultra-low power full adder circuit using SOI double-gate MOSFET devices

2008 ◽  
Vol 44 (18) ◽  
pp. 1095 ◽  
Author(s):  
I. Hassoune ◽  
X. Yang ◽  
I. O'Connor ◽  
D. Navarro
Keyword(s):  
Low Power ◽  
Full Adder ◽  
Double Gate ◽  
Ultra Low Power ◽  
Double Gate Mosfet

DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY

2013 ◽  
Vol 12 (06) ◽  
pp. 1350042
Author(s):  
ANUJ KUMAR SHRIVASTAVA ◽  
SHYAM AKASHE
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Full Adder ◽  
Basic Block ◽  
Double Gate ◽  
Arithmetic Circuit ◽  
Double Gate Mosfet ◽  
Rf Devices ◽  
Power Application ◽  
Circuit Technique

Full adder is the basic block of arithmetic circuit found in microcontroller and microprocessor inside arithmetic and logic unit (ALU). Improving the performance of the adder is essential for upgrading the performance of digital electronics circuit where adder is employed. In this paper, a single bit full adder circuit has been designed with the help of double gate (MOSFET), the used parameters value has been varied significantly for improving the performance of full adder circuit. Double gate transistor circuit considers as a promising candidate for low power application domain as well as used in radio frequency (RF) devices. Multi-threshold CMOS (MTCMOS) is the most used circuit technique to reduce the leakage current in idle circuit. In this paper, different parameters are analyzed on MTCMOS Technique. MTCMOS technique achieves 99.6% reduction of leakage current, active power is reduced by 42.64% and delay is reduced by 71.9% as compared with conventional double gate 14T full adder. Simulation results of double gate full adder have been performed on cadence virtuoso tool with 45 nm technology.

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