Ultra-low power full adder circuit using SOI double-gate MOSFET devices

2008 ◽  
Vol 44 (18) ◽  
pp. 1095 ◽  
Author(s):  
I. Hassoune ◽  
X. Yang ◽  
I. O'Connor ◽  
D. Navarro
Keyword(s):  
Low Power ◽  
Full Adder ◽  
Double Gate ◽  
Ultra Low Power ◽  
Double Gate Mosfet

DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY

2013 ◽  
Vol 12 (06) ◽  
pp. 1350042
Author(s):  
ANUJ KUMAR SHRIVASTAVA ◽  
SHYAM AKASHE
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Full Adder ◽  
Basic Block ◽  
Double Gate ◽  
Arithmetic Circuit ◽  
Double Gate Mosfet ◽  
Rf Devices ◽  
Power Application ◽  
Circuit Technique

Full adder is the basic block of arithmetic circuit found in microcontroller and microprocessor inside arithmetic and logic unit (ALU). Improving the performance of the adder is essential for upgrading the performance of digital electronics circuit where adder is employed. In this paper, a single bit full adder circuit has been designed with the help of double gate (MOSFET), the used parameters value has been varied significantly for improving the performance of full adder circuit. Double gate transistor circuit considers as a promising candidate for low power application domain as well as used in radio frequency (RF) devices. Multi-threshold CMOS (MTCMOS) is the most used circuit technique to reduce the leakage current in idle circuit. In this paper, different parameters are analyzed on MTCMOS Technique. MTCMOS technique achieves 99.6% reduction of leakage current, active power is reduced by 42.64% and delay is reduced by 71.9% as compared with conventional double gate 14T full adder. Simulation results of double gate full adder have been performed on cadence virtuoso tool with 45 nm technology.

32 nm high current performance double gate MOSFET for low power CMOS circuits

2014 ◽  
Vol 102 (3) ◽  
pp. 347-361
Author(s):  
Morteza Rahimian ◽  
Ali A. Orouji ◽  
Amirhossein Aminbeidokhti
Keyword(s):  
Low Power ◽  
Cmos Circuits ◽  
Double Gate ◽  
High Current ◽  
Double Gate Mosfet ◽  
Low Power Cmos

Analytical Model of Double Gate MOSFET for High Sensitivity Low Power Photosensor

2013 ◽  
Vol 13 (5) ◽  
pp. 500-510 ◽  
Author(s):  
Rajni Gautam ◽  
Manoj Saxena ◽  
R.S. Gupta ◽  
Mridula Gupta
Keyword(s):  
Low Power ◽  
Analytical Model ◽  
High Sensitivity ◽  
Double Gate ◽  
Double Gate Mosfet

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

2020 ◽  
Vol 10 (4) ◽  
pp. 457-470 ◽  
Author(s):  
Dipanjan Sen ◽  
Savio J. Sengupta ◽  
Swarnil Roy ◽  
Manash Chanda ◽  
Subir K. Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Dominant Factor ◽  
Double Gate ◽  
Cmos Inverter ◽  
Ultra Low Power ◽  
Voltage Swing

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

Sign in / Sign up

Export Citation Format

Share Document