Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs

2014 ◽  
Vol E97.A (2) ◽  
pp. 675-678
Author(s):  
Hiroshi NINOMIYA ◽  
Manabu KOBAYASHI ◽  
Yasuyuki MIURA ◽  
Shigeyoshi WATANABE
Keyword(s):  
Circuit Design ◽  
Double Gate ◽  
Reconfigurable Circuit ◽  
Arithmetic Logic Unit ◽  
Logic Unit

Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

2017 ◽  
Vol 9 (4) ◽  
pp. 04018-1-04018-4
Author(s):  
K. Nehru ◽  
◽  
T. Nagarjuna ◽  
G. Vijay ◽  
◽  
...  
Keyword(s):  
Comparative Analysis ◽  
Arithmetic Logic Unit ◽  
Logic Unit

Improving Performance of a Multi-Bit Arithmetic Logic Unit

2021 ◽  
Vol 26 (1) ◽  
pp. 40-53
Author(s):  
A.N. Yakunin ◽  
◽  
Aung Myo San ◽  
Khant Win ◽  
◽  
...  
Keyword(s):  
High Speed ◽  
Operating Time ◽  
Arithmetic Logic Unit ◽  
Maximum Delay ◽  
Sequential Organization ◽  
Quartus Ii ◽  
Logic Unit

In modern microprocessors to reduce the time resources the arithmetic-logic units (ALU) with an increased organization of arithmetic carry, characterized by high speed, compared to ALU with sequential organization of the arithmetic carry, are commonly used. However, while increasing the bit number of the input operands, the operating time of ALU of ALU with the accelerated arithmetic carry increases linearly depending on the number of bits. Therefore, the development of ALU, providing higher performance than the existing known solutions, is an actual task. In this work the analysis of ALU with sequential and accelerated organization of the arithmetic carry has been performed. To increase the speed of the operation, a multi-bit ALU has been developed. The simulation of ALU circuits has been executed in Altera Quartus –II CAD environment. The comparison has been performed by the number of logical elements and the maximum delay as a result of modeling the ALU circuits for 4, 8, 16, 32, and 64 bits. A scheme for checking the results has been implemented to confirm the reliability of developed ALU. As a result, it has been found that when performing operations with the 64-bit operands, the developed ALU reduces the maximum delay by 53 % compared to ALU with sequential arithmetic carry and by 35.5 % compared to ALU with the accelerated arithmetic carry, respectively.

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