scholarly journals Design and Implementation of Low Power 32 Bit Arithmetic Logic Unit

2017 ◽  
Vol 166 (7) ◽  
pp. 14-17
Author(s):  
Nazia Khan ◽  
Pankaj Soni
Keyword(s):  
Low Power ◽  
Design And Implementation ◽  
Arithmetic Logic Unit ◽  
Logic Unit

scholarly journals A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 6876-6889 ◽  
Author(s):  
Prashanth Barla ◽  
Vinod Kumar Joshi ◽  
Somashekara Bhat
Keyword(s):  
Low Power ◽  
Cmos Circuit ◽  
Arithmetic Logic Unit ◽  
Logic Unit

scholarly journals A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic

2015 ◽  
Vol 11 (2) ◽  
pp. 104
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Reversible Logic ◽  
Low Loss ◽  
Arithmetic Logic Unit ◽  
Novel Approach ◽  
Cmos Design ◽  
Binary Arithmetic ◽  
Low Power Cmos ◽  
Logic Unit

Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) using optimized 8:1 multiplexer circuit with reversible logic concept [1]. This ALU circuit can perform complement, transfer, addition, subtraction, multiplication, OR, XOR, NAND functions on given values. The ALU circuit has been simulated on Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency. This 2-bit ALU using reversible logic is useful for the designs of low power loss systems.

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