Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique

2011 ◽  
Vol E94-C (1) ◽  
pp. 80-88 ◽  
Author(s):  
Yuji OSAKI ◽  
Tetsuya HIROSE ◽  
Kei MATSUMOTO ◽  
Nobutaka KUROKI ◽  
Masahiro NUMA
Keyword(s):  
Circuit Design ◽  
Supply Voltage ◽  
Digital Circuit ◽  
Voltage Scaling ◽  
Scaling Technique ◽  
Digital Circuit Design ◽  
Subthreshold Cmos ◽  
Supply Voltage Scaling ◽  
On Chip

scholarly journals Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1718
Author(s):  
Neha Gupta ◽  
Ambika Prasad Shah ◽  
Sajid Khan ◽  
Santosh Kumar Vishvakarma ◽  
Michael Waltl ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Functional Improvement ◽  
Scaling Technique ◽  
Iot Applications ◽  
Sram Cell ◽  
Improved Stability ◽  
Supply Voltage Scaling ◽  
Power Delay Product

This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

2008 ◽  
Vol 96 (2) ◽  
pp. 343-365 ◽  
Author(s):  
B.H. Calhoun ◽  
Yu Cao ◽  
Xin Li ◽  
Ken Mai ◽  
L.T. Pileggi ◽  
...  
Keyword(s):  
Circuit Design ◽  
Digital Circuit ◽  
Nanoscale Cmos ◽  
Digital Circuit Design ◽  
Challenges And Opportunities ◽  
Design Challenges

A MOS Transistor Model for Mixed Analog-digital Circuit Design and Simulation

2006 ◽  
pp. 49-95 ◽  
Author(s):  
Matthias Bucher ◽  
Christophe Lallement ◽  
François Krummenacher ◽  
Christian Enz
Keyword(s):  
Circuit Design ◽  
Digital Circuit ◽  
Mos Transistor ◽  
Digital Circuit Design ◽  
Transistor Model
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