scholarly journals Efficient motion vector prediction scheme for high speed motion estimation in H.264/AVC

2008 ◽  
Vol 5 (21) ◽  
pp. 889-894
Author(s):  
Jinha Choi ◽  
Wonjae Lee ◽  
Yunho Jung ◽  
Jaeseok Kim
Keyword(s):  
Motion Estimation ◽  
High Speed ◽  
Motion Vector ◽  
Prediction Scheme ◽  
Motion Vector Prediction

An Efficient Hardware-Oriented Algorithm of Spatial Motion Vector Prediction for AVS HD Video Encoder

2014 ◽  
Vol 556-562 ◽  
pp. 4365-4371
Author(s):  
Ming Hui Yang ◽  
Xiao Dong Xie
Keyword(s):  
Motion Estimation ◽  
Motion Vector ◽  
Spatial Motion ◽  
Coding Efficiency ◽  
Multi Stage ◽  
Macro Block ◽  
Optimal Coding ◽  
Adjacent Block ◽  
Left Block ◽  
Motion Vector Prediction

Motion Vector Prediction (MVP) plays an important role in improving coding efficiency in HEVC, H.264/AVC and AVS video coding standard. MVP is implemented by exploiting redundancy of adjacent-block optimal coding information under the constraint that MVP must be performed in a serial way. The constraint prevents parallel processing and MB pipeline based on LevelC+. In multi-stage pipeline, to some extent, adjacent-block best mode-decision information can hardly be obtained. In this paper, we propose a new hardware-oriented method to improve the coding performance at a cost of few hardware resources. When adjacent block is not available, spatial motion vector prediction (SMVP) for integer motion estimation (IME) and fraction motion estimation (FME) will take the IME best mode information and FME best mode information of left block as best information to derive PMV (Predicted Motion Vector) for current macro-block or block. Experimental results shows that the method we propose can achieve a better performance than the existing methods by 0.1db for the cases with intense movement and a non-degrading performance for flat cases.

scholarly journals Fully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion Estimation

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-8
Author(s):  
Reeba Korah ◽  
J.Raja Paul Perinbam
Keyword(s):  
Motion Estimation ◽  
High Speed ◽  
Motion Vector ◽  
Computational Cost ◽  
Parallel Architecture ◽  
Clock Frequency ◽  
Processing Elements ◽  
Parallel Design ◽  
Search Approach ◽  
Coarse To Fine

This paper presents a low power and high speed architecture for motion estimation with Candidate Block and Pixel Subsampling (CBPS) Algorithm. Coarse-to-fine search approach is employed to find the motion vector so that the local minima problem is totally eliminated. Pixel subsampling is performed in the selected candidate blocks which significantly reduces computational cost with low quality degradation. The architecture developed is a fully pipelined parallel design with 9 processing elements. Two different methods are deployed to reduce the power consumption, parallel and pipelined implementation and parallel accessing to memory. For processing 30 CIF frames per second our architecture requires a clock frequency of 4.5 MHz.

Sign in / Sign up

Export Citation Format

Share Document