scholarly journals Fully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion Estimation

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-8
Author(s):  
Reeba Korah ◽  
J.Raja Paul Perinbam
Keyword(s):  
Motion Estimation ◽  
High Speed ◽  
Motion Vector ◽  
Computational Cost ◽  
Parallel Architecture ◽  
Clock Frequency ◽  
Processing Elements ◽  
Parallel Design ◽  
Search Approach ◽  
Coarse To Fine

This paper presents a low power and high speed architecture for motion estimation with Candidate Block and Pixel Subsampling (CBPS) Algorithm. Coarse-to-fine search approach is employed to find the motion vector so that the local minima problem is totally eliminated. Pixel subsampling is performed in the selected candidate blocks which significantly reduces computational cost with low quality degradation. The architecture developed is a fully pipelined parallel design with 9 processing elements. Two different methods are deployed to reduce the power consumption, parallel and pipelined implementation and parallel accessing to memory. For processing 30 CIF frames per second our architecture requires a clock frequency of 4.5 MHz.

scholarly journals Efficient motion vector prediction scheme for high speed motion estimation in H.264/AVC

2008 ◽  
Vol 5 (21) ◽  
pp. 889-894
Author(s):  
Jinha Choi ◽  
Wonjae Lee ◽  
Yunho Jung ◽  
Jaeseok Kim
Keyword(s):  
Motion Estimation ◽  
High Speed ◽  
Motion Vector ◽  
Prediction Scheme ◽  
Motion Vector Prediction

scholarly journals BlockNet: A Deep Neural Network for Block-Based Motion Estimation Using Representative Matching

Symmetry ◽  
2020 ◽  
Vol 12 (5) ◽  
pp. 840
Author(s):  
Junggi Lee ◽  
Kyeongbo Kong ◽  
Gyujin Bae ◽  
Woo-Jin Song
Keyword(s):  
Motion Estimation ◽  
Computational Cost ◽  
Frame Rate ◽  
Global Motion ◽  
Neural Architecture ◽  
Block Motion ◽  
Block Based ◽  
Frame Rate Up Conversion ◽  
Coarse To Fine ◽  
Simple Average

Owing to the limitations of practical realizations, block-based motion is widely used as an alternative for pixel-based motion in video applications such as global motion estimation and frame rate up-conversion. We hereby present BlockNet, a compact but effective deep neural architecture for block-based motion estimation. First, BlockNet extracts rich features for a pair of input images. Then, it estimates coarse-to-fine block motion using a pyramidal structure. In each level, block-based motion is estimated using the proposed representative matching with a simple average operator. The experimental results show that BlockNet achieved a similar average end-point error with and without representative matching, whereas the proposed matching incurred 18% lower computational cost than full matching.

An Optimized Approach to Pipelined Architecture for Fast 2D Normalized Cross-Correlation

2019 ◽  
Vol 28 (12) ◽  
pp. 1950211 ◽  
Author(s):  
R. E. Chaudhari ◽  
S. B. Dhok
Keyword(s):  
High Speed ◽  
Cross Correlation ◽  
Computational Cost ◽  
Block Size ◽  
Computation Time ◽  
Object Localization ◽  
Clock Frequency ◽  
Image Block ◽  
Normalized Cross Correlation ◽  
Pipelined Architecture

An optimized hardware architecture for fast normalized cross-correlation (NCC) is essential in real-time high-speed applications. Typical applications of NCC are in object localization, as one of the best motion estimators and as a similarity measure in the field of image processing. However, high computational cost is a significant drawback of NCC. To reduce computation time and hardware resource usages, this paper presents a feed-forward single-path architecture with parallel computation of numerator and denominator components of NCC. The cross-correlation of two signals is implemented in the frequency domain using pipelined architecture of 2D FFT with polyphase sequential subband decomposition technique. The FFT can be determined for any even length of signal when compared to the traditional method involving a power of two-signal length. The proposed pipelined architecture of NCC is more efficient in terms of computational complexity and memory requirement. This proposed architecture is implemented in Verilog HDL with fixed-point data type which helps to devise simple and efficient architecture, which gives excellent SQNR of more than 90 dB with 22-bit output word length. It can operate at the maximum clock frequency of 220.4[Formula: see text]MHz, takes a total NCC time of 4.36[Formula: see text][Formula: see text]s and has a latency of 996 cycles, giving a throughput of 220 Msamples/s for a block size of [Formula: see text] pixels using Virtex-7 FPGA. This pipelined architecture not only offers an attractive solution for different sizes of image block, but also improves the speed of the system.

Robust visual tracking via randomly projected instance learning

2017 ◽  
Vol 10 (3) ◽  
pp. 258-271
Author(s):  
Fei Cheng ◽  
Kai Liu ◽  
Mao-Guo Gong ◽  
Kaiyuan Fu ◽  
Jiangbo Xi
Keyword(s):  
Real Time ◽  
High Speed ◽  
Design Methodology ◽  
Search Strategy ◽  
Multiple Instance Learning ◽  
Appearance Model ◽  
Robust Tracking ◽  
Content Type ◽  
Search Approach ◽  
Coarse To Fine

Purpose The purpose of this paper is to design a robust tracking algorithm which is suitable for the real-time requirement and solves the mistake labeling issue in the appearance model of trackers with the spare features. Design/methodology/approach This paper proposes a tracker to select the most discriminative randomly projected ferns and integrates a coarse-to-fine search strategy in this framework. First, the authors exploit multiple instance boosting learning to maximize the bag likelihood and select randomly projected fern from feature pool to degrade the effect of mistake labeling. Second, a coarse-to-fine search approach is first integrated into the framework of multiple instance learning (MIL) for less detections. Findings The quantitative and qualitative experiments demonstrate that the tracker has shown favorable performance in efficiency and effective among the competitors of tracking algorithms. Originality/value The proposed method selects the feature from the compressive domain by MIL AnyBoost and integrates the coarse-to-fine search strategy first to reduce the burden of detection. This paper designs a tracker with high speed and favorable results which is more suitable for real-time scene.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

scholarly journals A Joint 2D-3D Complementary Network for Stereo Matching

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1430
Author(s):  
Xiaogang Jia ◽  
Wei Chen ◽  
Zhengfa Liang ◽  
Xin Luo ◽  
Mingfei Wu ◽  
...  
Keyword(s):  
Stereo Matching ◽  
Computational Cost ◽  
Research Field ◽  
Disparity Map ◽  
Improve Performance ◽  
Cost Aggregation ◽  
Disparity Range ◽  
Public Datasets ◽  
Coarse To Fine ◽  
Speed And Accuracy

Stereo matching is an important research field of computer vision. Due to the dimension of cost aggregation, current neural network-based stereo methods are difficult to trade-off speed and accuracy. To this end, we integrate fast 2D stereo methods with accurate 3D networks to improve performance and reduce running time. We leverage a 2D encoder-decoder network to generate a rough disparity map and construct a disparity range to guide the 3D aggregation network, which can significantly improve the accuracy and reduce the computational cost. We use a stacked hourglass structure to refine the disparity from coarse to fine. We evaluated our method on three public datasets. According to the KITTI official website results, Our network can generate an accurate result in 80 ms on a modern GPU. Compared to other 2D stereo networks (AANet, DeepPruner, FADNet, etc.), our network has a big improvement in accuracy. Meanwhile, it is significantly faster than other 3D stereo networks (5× than PSMNet, 7.5× than CSN and 22.5× than GANet, etc.), demonstrating the effectiveness of our method.

An Efficient Match Search Approach Using Two-Dimensional Hash Function in Hardware-Based Dictionary Compression

2019 ◽  
Vol 28 (06) ◽  
pp. 1950106
Author(s):  
Qian Dong ◽  
Bing Li
Keyword(s):  
Compression Ratio ◽  
Hash Function ◽  
High Speed ◽  
Two Dimensional ◽  
Time Data ◽  
Search Result ◽  
Compression Speed ◽  
Real Time Data ◽  
Real Time Data Processing ◽  
Search Approach

The hardware-based dictionary compression is widely adopted for high speed requirement of real-time data processing. Hash function helps to manage large dictionary to improve compression ratio but is prone to collisions, so some phrases in match search result are not true matches. This paper presents a novel match search approach called dual chaining hash refining, which can improve the efficiency of match search. From the experimental results, our method showed obvious advantage in compression speed compared with other approach that utilizes single hash function described in the previous publications.

scholarly journals Mechanical and Electronic Video Stabilization Strategy of Mortars with Trajectory Correction Fuze Based on Infrared Image Sensor

Sensors ◽  
2020 ◽  
Vol 20 (9) ◽  
pp. 2461 ◽  
Author(s):  
Cong Zhang ◽  
Dongguang Li
Keyword(s):  
Motion Vector ◽  
Computational Cost ◽  
Infrared Image ◽  
Image Sensor ◽  
Projection Algorithm ◽  
Video Stabilization ◽  
Sensors And Actuators ◽  
Simulation And Experiment ◽  
Transformation Relation ◽  
Trajectory Correction

For a higher attack accuracy of projectiles, a novel mechanical and electronic video stabilization strategy is proposed for trajectory correction fuze. In this design, the complexity of sensors and actuators were reduced. To cope with complex combat environments, an infrared image sensor was used to provide video output. Following the introduction of the fuze’s workflow, the limitation of sensors for mechanical video stabilization on fuze was proposed. Particularly, the parameters of the infrared image sensor that strapdown with fuze were calculated. Then, the transformation relation between the projectile’s motion and the shaky video was investigated so that the electronic video stabilization method could be determined. Correspondingly, a novel method of dividing sub-blocks by adaptive global gray threshold was proposed for the image pre-processing. In addition, the gray projection algorithm was used to estimate the global motion vector by calculating the correlation between the curves of the adjacent frames. An example simulation and experiment were implemented to verify the effectiveness of this strategy. The results illustrated that the proposed algorithm significantly reduced the computational cost without affecting the accuracy of the motion estimation. This research provides theoretical and experimental basis for the intelligent application of sensor systems on fuze.

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