A Comparison of RTO and Furnace Oxides

1987 ◽  
Vol 92 ◽  
Author(s):  
Marie E. Burnham ◽  
Ronald N. Legge ◽  
Jaim Nulman Jaim Nulman ◽  
Peter L. Fejes ◽  
James F. Brown
Keyword(s):  
Heat Treatments ◽  
Constant Current ◽  
Trapping Rate ◽  
Gate Oxides ◽  
Original Intent ◽  
Non Volatile Memory ◽  
Higher Temperature ◽  
Wafer Processing ◽  
Substrate Defects ◽  
Field Oxide

ABSTRACTThe original intent of this study was to compare rapid thermal, thin (80-100Å) gate oxides with standard, furnace-grown, thin gate oxides for endurance. Wafer processing before gate oxide growth was chosen to duplicate processing used ina typical non-volatile memory product. In particular, care was taken to duplipate pre- and post- gate growth processing of field oxide isolated polysilicon capacitors for all wafers in order to eliminate the previous difficulties in comparing oxides when different cleans and processing steps are used.[1] Substrate defects, atypical to this process, were presumably introduced during the initial wafer cleaning and scattered the time-to-breakdown (TTB) values during a constant current stress of these oxides to the point where statistical comparison of TTB averages was dubious. However, for unannealed wafers and for post polysilicon definition heat treatments of 900°C, RTO oxides grown with HCL had the same oxide trapping rate as the furnace oxides grown with TCA and RTO oxides grown in pure O2 had a faster trapping rate. Higher temperature post polysilicon definition heat treatments had different effects. RTO oxides exhibited better yield than the furnace oxides. These results illustrate the differences between RTO and furnace oxidation in the presence of non-ideal wafer substrates.

Characterization of Er/O-doped Si-LEDs with Low Thermal Quenching

2005 ◽  
Vol 866 ◽  
Author(s):  
A. Karim ◽  
W.-X. Ni ◽  
A. Elfving ◽  
P.O.Å. Persson ◽  
G.V. Hansson
Keyword(s):  
Temperature Dependence ◽  
Reverse Bias ◽  
Thermal Quenching ◽  
Constant Current ◽  
Cross Sectional ◽  
Transmission Electron ◽  
Low Energy Electrons ◽  
Higher Temperature ◽  
Electron Emitters

AbstractElectroluminescence studies of MBE-grown Er/O-doped Si-diodes at reverse bias have been done. For some devices there is much reduced thermal quenching of the emission at 1.54 νm. There are examples where the temperature dependence is abnormal in that the intensity for a constant current even increases with temperature up to e.g. 80 °C. These devices have been studied with cross-sectional transmission electron microscopy to see the microstructure of the Er/O-doped layers as well as the B-doped SiGe-layers that are used as electron emitters during reverse bias. Although there are defects in the layers there is no evidence for large thick precipitates of SiO2. While reduced thermal quenching often is attributed to having the Er-ions within SiO2 layers, this is not the case for our structures as evidenced by our TEM-studies. The origin of the abnormal temperature dependence is attributed to the two mechanisms of breakdown in the reverse-biased diodes. At low temperature the breakdown current is mainly due to avalanche resulting in low-energy electrons and holes that quenches the intensity by Auger deexcitation of the Er-ions. At higher temperature the breakdown current is mainly phonon-assisted tunneling which results in a more efficient pumping with less de-excitation of the Er-ions. Finally at the highest temperatures the thermal quenching sets in corresponding to an activation energy of 125 meV, which is slightly lower than 150 meV that has been reported in other studies.

Stress induced leakage current in ultra-thin gate oxides after constant current stress

1997 ◽  
Vol 36 (1-4) ◽  
pp. 145-148 ◽  
Author(s):  
A. Scarpa ◽  
G. Ghibaudo ◽  
G. Ghidini ◽  
G. Pananakakis ◽  
A. Paccagnella
Keyword(s):  
Leakage Current ◽  
Constant Current ◽  
Gate Oxides ◽  
Current Stress ◽  
Stress Induced Leakage Current

Effect of heat sums and of heat applied separately to shoots and roots on flowering in potted Piceaglauca grafts

1991 ◽  
Vol 21 (5) ◽  
pp. 672-679 ◽  
Author(s):  
Stephen D. Ross
Keyword(s):  
Heat Treatments ◽  
Root Activity ◽  
Strongly Correlated ◽  
Root Temperature ◽  
Consistent Effect ◽  
Flowering Response ◽  
Greenhouse Experiments ◽  
Temperature Requirement ◽  
Higher Temperature ◽  
The Relationship

Two greenhouse experiments (1985, 1987) investigated the relationship between flowering and root activity in gibberellin A4/7 treated, potted Piceaglauca (Moench) Voss grafts subjected to heat (30 vs. 20 °C in 1985, 25 vs. 18 °C in 1987) applied separately to shoots and roots for 3 or 4 weeks during the period of cone-bud differentiation. Heat applied to roots significantly reduced the percentage of white-tipped roots during this period but had no effect on seed or pollen cones produced. Heat applied to shoots, which had no consistent effect on root activity, promoted flowering independent of root temperature. These results suggest that the flowering response to heat in P. glauca is mediated through the shoot, and not by retarding root activity as has been proposed. A third experiment (1988), in which entire grafts were exposed to heat treatments of 20, 25, or 30 °C for 5 or 10 h per day, disclosed a higher temperature requirement for maximizing pollen cones (10 h at 30 °C) than for maximizing seed cones (5 h at 20 °C). Male flowering was strongly correlated with the daily sum of degrees per hour above 10 °C.

Reliability of Gate Oxides on 4H-SiC Epitaxial Surface Planarized by CMP Treatment

2014 ◽  
Vol 778-780 ◽  
pp. 545-548 ◽  
Author(s):  
Keiichi Yamada ◽  
Osamu Ishiyama ◽  
Kentaro Tamura ◽  
Tamotsu Yamashita ◽  
Atsushi Shimozato ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Constant Current ◽  
Wafer Surface ◽  
Gate Oxides ◽  
Mos Capacitor ◽  
Current Time ◽  
Time Dependent Dielectric Breakdown ◽  
High Uniformity ◽  
Current Voltage ◽  
Differential Interference Microscope

This work reports about effect of SiC epitaxial-wafer surface planarization by chemo-mechanical polishing (CMP) treatment on electrical properties of SiC-MOS capacitor. We have observed the surface morphology of 4H-SiC epitaxial layer planarized by CMP treatment using a confocal differential interference microscope, and evaluated the reliability of gate oxides on this surface using constant current time-dependent dielectric breakdown (CC-TDDB) and current-voltage (I-V) characteristics. Surface roughness such as step bunching deteriorates drastically the reliability of gate oxide, while the epitaxial-surface planarization by CMP treatment improved oxide reliability due to the high uniformity of the oxide film thickness.

Influence of Phosphorous Auto-Doping on the Characteristics of SiO2/SiC Gate Dielectrics

2015 ◽  
Vol 821-823 ◽  
pp. 492-495
Author(s):  
Ming Hung Weng ◽  
A.E. Murphy ◽  
Craig Ryan ◽  
B.J.D. Furnival ◽  
Dave A. Smith ◽  
...  
Keyword(s):  
High Temperature ◽  
Gate Dielectrics ◽  
Constant Current ◽  
Conduction Band Edge ◽  
Flat Band ◽  
Stress Tests ◽  
Oxide Interface ◽  
Band Shift ◽  
Bias Stress ◽  
Field Oxide

We present the influence of phosphorous auto-doping on the characteristics of the oxide interface in 4H-SiC following high temperature gate oxide annealing. IV characteristics show no evidence of direct tunnelling breakdown; however Fowler Nordheim (F-N) conduction is observed in high electric field with the oxides able to sustain >10MV/cm. Capacitance Voltage data show DIT <1x1012 eV-1cm-2 close to the conduction band edge after POA, with undoped samples demonstrating DIT below 5x1011 eV-1cm-2. Photo CV data indicates smaller flat band voltage shifts of 0.6V at midpoint for the undoped samples, in comparison to 0.9V for the phosphorous doped devices. Temperature and bias stress tests at 200°C showed marginal hysteresis (0.3V) in both wafers. Reliability of time-dependent constant current and constant voltage characteristics revealed higher TDDB lifetimes in the undoped wafer. We conclude that the unintentional incorporation of phosphorous into the gate stack as a result of high temperature POA of the doped field oxide leads to a variation in flat band shift, higher DIT, and lower dielectric reliability.

Comparison between SiO2 Films and Nitridated Oxides in N2O Ambient in Terms of Bulk/Interface Trapping Properties

1994 ◽  
Vol 338 ◽  
Author(s):  
Constantin Papadas ◽  
Patrick Mortini
Keyword(s):  
Gate Oxides ◽  
Sio2 Films ◽  
Degradation Data ◽  
Nitridation Process ◽  
Advanced Technologies ◽  
Optimum Selection ◽  
Non Volatile Memory ◽  
Thermal Nitridation ◽  
Physical Degradation ◽  
Selection Of

ABSTRACTThe necessity of employing nitridation process in advanced technologies will be underlined. The different technological alternatives for preparing oxinitride layers will be traced back, followed by a review of the methods currently available for assessing the degradation features of the Si/SiO2 system. Furthermore, comparison between pure SiO2 layers and nitridated films in N2O ambient will be conducted in terms of bulk/interface trapping properties and the obtained physical degradation data will be correlated with classical reliability results. Large emphasis will be given on the trapping properties of tunnel oxides used in non—volatile memory arrays and different technological alternatives will be exploited (i.e. Rapid Thermal Nitridation, Furnace Nitridation). In addition, a similar analysis will be carried out for gate oxides. Finally, some guidelines concerning the optimum selection of the furnace nitridation conditions will be given.

Low Temperature (850 °C) Two-Step N2O Annealed Thin Gate Oxides

1996 ◽  
Vol 428 ◽  
Author(s):  
Chao Sung Lai ◽  
Chung Len Lee ◽  
Tan Fu Lei ◽  
Tien Sheng Chao ◽  
Chun Hung Peng ◽  
...  
Keyword(s):  
Low Temperature ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Interface State ◽  
Constant Current ◽  
Short Channel ◽  
Gate Oxides ◽  
Current Stressing ◽  
State Generation

AbstractThe electrical characteristics of thin gate dielectrics prepared by low temperature (850 °C) two-step N20 nitridation (LTN) process are presented. The gate oxides were grown by wet oxidation at 800 °C and then annealed in N2O at 850 °C. The oxide with N2O anneal, even for low temperature (850 °C), had nitrogen incorporation at oxide/silicon interface. The charge trapping phenomena and interface-state generation (ΔDitm) induced by constant current stressing were reduced and charge-to-breakdown (Qbd) under constant current stressing was increased. This LTN oxynitride was used as gate dielectric for N-channel MOSFET, whose hot-canrier immunity was shown improved and reverse short channel effect (RSCE) was suppressed.

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