Highly Reliable Metal Gate nMOSFETs by Improved CVD-WSix films with Work Function of 4.3eV

2004 ◽  
Vol 811 ◽  
Author(s):  
Kazuaki Nakajima ◽  
Hiroshi Nakazawa ◽  
Katsuyuki Sekine ◽  
Kouji Matsuo ◽  
Tomohiro Saito ◽  
...  

ABSTRACTIn this paper, we first propose an improved CVD-WSix metal gate suitable for use with nMOSFETs. Work function of CVD-WSi3.9 gate estimated from C-V measurements was 4.3eV. The nMOSFET using CVD-WSi3.9 gate electrode showed that Vth variation of L/W=1 μm/10μm nMOSFETs can be suppressed to be lower than 8mV in 22chip. In CVD-WSi3.9 gate MOSFETs with gate length of 50nm, a drive current of 636μA/μm was achieved for off-state leakage current of 35nA/μm at 1.0V of power supply voltage. By using CVD-WSi3.9 gate electrode, highly reliable metal gate nMOSFETs can be realized.

2018 ◽  
Vol 32 (14) ◽  
pp. 1850176 ◽  
Author(s):  
Shoumian Chen ◽  
Enming Shang ◽  
Shaojian Hu

This paper introduces a device performance optimization approach for the FinFET through optimization of the gate length. As a result of reducing the gate length, the leakage current (I[Formula: see text]) increases, and consequently, the stress along the channel enhances which leads to an increase in the drive current (I[Formula: see text]) of the PMOS. In order to sustain I[Formula: see text], work function is adjusted to offset the effect of the increased stress. Changing the gate length of the transistor yields different drive currents when the leakage current is fixed by adjusting the work function. For a given device, an optimal gate length is found to provide the highest drive current. As an example, for a standard performance device with I[Formula: see text] = 1 nA/um, the best performance I[Formula: see text] = 856 uA/um is at L = 34 nm for 14 nm FinFET and I[Formula: see text] = 1130 uA/um at L = 21 nm for 7 nm FinFET. A 7 nm FinFET will exhibit performance boost of 32% comparing with 14 nm FinFET. However, applying the same method to a 5 nm FinFET, the performance boosting is out of expectance comparing to the 7 nm FinFET, which is due to the severe short-channel-effect and the exhausted channel stress in the FinFET.


2011 ◽  
Vol E94-C (6) ◽  
pp. 1072-1075
Author(s):  
Tadashi YASUFUKU ◽  
Yasumi NAKAMURA ◽  
Zhe PIAO ◽  
Makoto TAKAMIYA ◽  
Takayasu SAKURAI

2016 ◽  
Vol E99.C (10) ◽  
pp. 1219-1225
Author(s):  
Masahiro ISHIDA ◽  
Toru NAKURA ◽  
Takashi KUSAKA ◽  
Satoshi KOMATSU ◽  
Kunihiro ASADA

1993 ◽  
Vol 29 (15) ◽  
pp. 1324 ◽  
Author(s):  
L.E. Larson ◽  
M.M. Matloubian ◽  
J.J. Brown ◽  
A.S. Brown ◽  
M. Thompson ◽  
...  

2020 ◽  
Vol 67 (5) ◽  
pp. 811-817
Author(s):  
G. Torrens ◽  
A. Alheyasat ◽  
B. Alorda ◽  
S. Barcelo ◽  
J. Segura ◽  
...  

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