Optimization of Fluorine Co-implantation for PMOS Source and Drain Extension Formation for 65nm Technology Node

2004 ◽  
Vol 810 ◽  
Author(s):  
H. Graoui ◽  
M. Hilkene ◽  
B. McComb ◽  
M. Castle ◽  
S. Felch ◽  
...  
Keyword(s):  
Solubility Limit ◽  
Junction Depth ◽  
Solid Solubility Limit ◽  
Enhanced Diffusion ◽  
Technology Node ◽  
Energy Needs ◽  
Junction Formation ◽  
Boron Implantation ◽  
The Right ◽  
Spike Annealing

ABSTRACTThe main challenges for PMOS ultra shallow junction formation remain the transient enhanced diffusion (TED) and the solid solubility limit of boron in silicon. It has been demonstrated that low energy boron implantation and spike annealing are key in meeting the 90 nm technology node ITRS requirements. To meet the 65 nm technology requirements many studies have used fluorine co-implantation with boron and Si+ or Ge+ pre-amorphization (PAI) and spike annealing. Although using BF+2 can be attractive for its high throughput, self-amorphization and the presence of fluorine, many studies have shown that for the fluorine to successfully reduce TED its energy needs to be well optimized with respect to the boron's, therefore BF+2 does not present the right fluorine/boron energy ratio for the optimum junction formation. In this work we optimize the fluorine energy when a deep or shallow PAI is used. We also demonstrate that the fluorine dose needs to be carefully optimized otherwise a reverse effect can be observed. We will also show that the optimized junction depends less on the Ge+ energies between 2 keV and 20 keV and when HF etch is implemented after Ge+ PAI, improvements in both the junction depth and the sheet resistance are observed.

Low Temperature Shallow Junction Formation For 70nm Technology Node And Beyond

2002 ◽  
Vol 717 ◽  
Author(s):  
John O. Borland
Keyword(s):  
Low Temperature ◽  
Solubility Limit ◽  
Gate Stack ◽  
Solid Solubility Limit ◽  
Shallow Junction ◽  
Technology Node ◽  
Dopant Level ◽  
High K ◽  
Junction Formation ◽  
Low Power Cmos

AbstractLow temperature shallow junction formation is an attractive activation technique for 70nm technology node and beyond as it can easily be integrated into device structures that are formed using disposable spacer (reverse source drain extension formation) or low power CMOS devices using high-k/metal gate stack structures. Therefore, this paper will first review the shallow junction requirements as stated in the 2001 ITRS (international technology roadmap for semiconductors) and it's interpretation to ion implantation shallow junction formation for various dopant activation and annealing techniques. First high temperature (>1000°C) RTA spike, flash or sub-melt laser annealing techniques with oxide or oxynitride/polysilicon electrode gate stack structures will be discussed and its limitations to >8E19/cm3 boron electrically active dopant level due to boron solid solubility limit in silicon satisfying only the 100nm technology node requirement (2003). Next, higher temperature laser melt annealing (1200°C to 1400°C) will be discussed and it's applicability beyond 70nm node technology (2006) to 25nm node (2016) where boron solid solubility limit is up to 5E20/cm3. However, if high-k (HfO) dielectric/metal electrode gate stack structures are to be used starting at sub-100nm node in 2005 for low power CMOS then low temperature (>700°C) annealing must be used for shallow junction formation to prevent recrystallization and dielectric constant degradation. Using low temperature SPE (solid phase epitaxial regrowth) annealing techniques in the 550°C to 750°C for short anneal times of >5mins., shallow & abrupt junctions 8.0nm deep, >2.0nm/decade with up to 2.5E20/cm3 boron electrical active dopant level can be achieved satisfying the 25nm technology node (2016) requirements.

Understanding and Controlling Transient Enhanced Dopant Diffusion in Silicon

1994 ◽  
Vol 354 ◽  
Author(s):  
P.A. Stolk ◽  
H.-J. Gossmann ◽  
D.J. Eaglesham ◽  
D.C. Jacobson ◽  
H.S. Luftman ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Activation Energy ◽  
Solubility Limit ◽  
Solid Solubility Limit ◽  
Near Surface ◽  
Enhanced Diffusion ◽  
Defect Clusters ◽  
Transmission Electron ◽  
Junction Formation ◽  
B Doping

AbstractImplanted B and P dopants in Si exhibit transient enhanced diffusion (TED) during initial annealing which arises from the excess interstitials generated by the implant. In order to study the mechanisms of TED, we have used B doping marker layers in Si to probe the injection of interstitials from near-surface, non-amorphizing Si implants during annealing. The in-diffusion of interstitials is limited by trapping at impurities and has an activation energy of -3.5 eV. Substitutional C is the dominant trapping center with a binding energy of 2-2.5 eV. The high interstitial supersaturation adjacent to the implant damage drives substitutional B into metastable clusters at concentrations below the B solid solubility limit. Transmission electron microscopy shows that the interstitials driving TED are emitted from {311} defect clusters in the damage region at a rate which also exhibits an activation energy of 3.6 eV. The population of excess interstitials is strongly reduced by incorporating substitutional C in Si to levels of ∼1019/cm3 prior to ion implantation. This provides a promising method for suppressing TED, thus enabling shallow junction formation in future Si devices through dopant implantation.

Ultra Shallow Junction Formation by B+/BF2+ Implantation at Energy of 0.5 KEV

1998 ◽  
Vol 532 ◽  
Author(s):  
M. Kase ◽  
Y Kikuchi ◽  
H. Niwa ◽  
T. Kimura
Keyword(s):  
Junction Depth ◽  
Shallow Junction ◽  
Enhanced Diffusion ◽  
Transient Enhanced Diffusion ◽  
Junction Formation

ABSTRACTThis paper describes ultra shallow junction formation using 0.5 keV B+/BF2+ implantation, which has the advantage of a reduced channeling tail and no transient enhanced diffusion. In the case of l × 1014 cm−2, 0.5 keV BF2 implantation a junction depth of 19 nm is achieved after RTA at 950°C.

A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS

2003 ◽  
Vol 765 ◽  
Author(s):  
R. Lindsay ◽  
B. Pawlak ◽  
J. Kittl ◽  
K. Henson ◽  
C. Torregiani ◽  
...  
Keyword(s):  
Low Power ◽  
Thermal Annealing ◽  
Solid Solubility ◽  
Laser Annealing ◽  
Solid Phase ◽  
Conventional Approach ◽  
Junction Depth ◽  
Flash Annealing ◽  
Junction Formation ◽  
Spike Annealing

AbstractDue to integration concerns, the use of meta-stable junction formation approaches like laser thermal annealing (LTA), solid phase epitaxial regrowth (SPER), and flash annealing has largely been avoided for the 90nm CMOS node. Instead fast-ramp spike annealing has been optimised along with co-implantation to satisfy the device requirements, often with the help from thin offset spacers. However for the 65nm and 45nm CMOS node it is widely accepted that this conventional approach will not provide the required pMOS junctions, even with changes in the transistor architecture.In this work, we will compare junction performance and integratablity of fast-ramp spike, flash, SPER and laser annealing down to 45nm CMOS. The junction depth, abruptness and resistance offered by each approach are balanced against device uniformity, deactivation and leakage. Results show that the main contenders for the 45nm CMOS are SPER and flash annealing – but both have to be rigorously optimised for regrowth rates, amorphous positioning and dopant and co-implant profiles. From the two, SPER offers the best junction abruptness (<1nm/dec) with leakage suitable for low power applications, while the flash anneal has the benefit of higher solid solubility (>4E20at/cm3) and less transistor modifications. As expected, Ge and F co-implanted spike annealed junctions do not reach the 45nm node requirements. For full-melt LTA, poly deformation on isolation can be reduced but geometry effects result in unacceptable junction non-uniformity.

Implant Dose and Spike Anneal Temperature Relationships

2001 ◽  
Vol 669 ◽  
Author(s):  
K. K. Bourdelle ◽  
A. T. Fiory ◽  
H.-J. L. Gossmann ◽  
S. P. McCoy
Keyword(s):  
Sheet Resistance ◽  
Junction Depth ◽  
Enhanced Diffusion ◽  
Coupled Diffusion ◽  
Temperature Trends ◽  
Transient Enhanced Diffusion ◽  
Physically Based ◽  
Spike Anneal ◽  
Spike Annealing ◽  
Anneal Temperature

ABSTRACTThe method of ion implantation and spike annealing for preparing shallow junctions suitable for the extension regions bridging the channel and source/drain contacts of CMOS transistors are studied by annealing blanket implants. Junction depths at a given sheet resistance for low energy B implants are minimized for the combination of a fast ramp with a sharp-spike anneal. This is shown to be physically based on activation energy phenomenology. The fraction of electrically activated B is insensitive to implant dose, unlike the case of transient enhanced diffusion. Arsenic implants show higher activation fraction than comparably annealed P implants, without the large transient enhanced diffusion which is attributed to P and Si-interstitial coupled diffusion. For targeted sheet resistance and junction depth, spiking temperature trends lower with implant dose, concomitant with decreasing fraction of activated dopant.

Investigation of Lateral and Vertical Profiles Enhanced by Implantation

1995 ◽  
Vol 396 ◽  
Author(s):  
A. Mineji ◽  
K. Hamada ◽  
S. Saito
Keyword(s):  
Point Defects ◽  
Diffusion Control ◽  
High Dose ◽  
Vertical Profiles ◽  
Junction Depth ◽  
Shallow Junction ◽  
Enhanced Diffusion ◽  
Junction Formation ◽  
D Region ◽  
High Dose Implantation

AbstractIn shallow junction formation with junction depth below 0.1μm, enhanced diffusion control is essential. The purpose of this paper is to investigate the B enhanced diffusion by point defects, introduced by high dose implantation with amorphization. Ge ions were implanted to induce amorphization within the S/D region of pMOS. These results were compared with that of the B enhanced diffusion by point defects, induced by Si+ implant with non-amorphization. These results suggest that the B enhanced diffusion in lateral profiles is much smaller, compared with that in vertical profiles, when point defects were introduced by amorphization.

Phase Separation of β-SN in Strained, Compositionally Metastable Ge1-xSnx Alloys

1995 ◽  
Vol 398 ◽  
Author(s):  
Joshua W. Kriesel ◽  
Susanne M. Lee
Keyword(s):  
Phase Separation ◽  
Electron Microprobe ◽  
Rf Sputtering ◽  
Melting Behavior ◽  
Solubility Limit ◽  
X Ray Diffraction ◽  
Solid Solubility Limit ◽  
Transformation Mechanisms ◽  
Subsequent Phase ◽  
Kinetics Of

ABSTRACTUsing rf sputtering and post-deposition annealing in a differential scanning calorimeter (DSC), we manufactured bulk (4000 nm) films of crystalline Ge0.83Sn0.17. This Sn concentration is much greater than the solid solubility limit of Sn in Ge (x ≤ 0.01). Continued annealing thermally induces Sn phase separation from the alloy, limiting the ultimate attainable grain size in the metastable crystals. We examine, here, the mechanisms and kinetics of the processes limiting the size of the Ge0.83Sn0.17 polycrystals. From a combination of DSC, electron microprobe, and x-ray diffraction (XRD) measurements, we propose phase transformation mechanisms corresponding to crystallization of amorphous Ge0.83Sn0.17, crystallization of an as-yet unidentified phase of Sn, and phase separation of Sn from the Ge1-xSnx crystals. We were unable to observe the unidentified phase of Sn in XRD, but the phase must be present in the material to account for the quantitative discrepancies (as much as 8 at.%) in Sn percentages determined from each of the DSC, XRD, and electron microprobe measurements. Our models for the various transformation kinetics were corroborated by the subsequent phase-separated Sn melting behavior observed in the DSC: two Sn melting endotherms, one of which was 20–100°C lower than the bulk melting temperature of Sn. This depressed temperature endotherm we speculate represents liquefaction of nanometer-sized (β–Sn clusters.

Positron annihilation study on the solid solubility limit of neodymium in pure iron

1985 ◽  
Vol 19 (1) ◽  
pp. 79-82 ◽  
Author(s):  
He You ◽  
Chang Xiang-rong ◽  
Tian Zhong-zhuo ◽  
Hsiao Chi-mei ◽  
Wang Ming-hua ◽  
...  
Keyword(s):  
Positron Annihilation ◽  
Solid Solubility ◽  
Pure Iron ◽  
Solubility Limit ◽  
Solid Solubility Limit ◽  
Positron Annihilation Study

Low energy boron implantation profiles in silicon from junction depth measurements

1971 ◽  
Vol 7 (1-2) ◽  
pp. 7-15 ◽  
Author(s):  
P. Sebillotte ◽  
M. Badanoiu ◽  
V. B. Ndocko ◽  
P. Siffert
Keyword(s):  
Low Energy ◽  
Junction Depth ◽  
Boron Implantation
Sign in / Sign up

Export Citation Format

Share Document