Signal Propagation and Multiplexing Challenges in Electronic Textiles

2002 ◽  
Vol 736 ◽  
Author(s):  
J. F. Muth ◽  
E. Grant ◽  
K. A. Luthy ◽  
L. S. Mattos ◽  
J. C. Braly ◽  
...  
Keyword(s):  
Optical Fibers ◽  
Transmission Lines ◽  
Large Scale ◽  
Printed Circuit Board ◽  
Signal Propagation ◽  
Circuit Board ◽  
Electrical Performance ◽  
Electronic Textiles ◽  
Electrical Transmission ◽  
Distributed Sensors

ABSTRACTWeaving, knitting or placing electronic circuits within a textile matrix offer exciting possibilities for large-scale conformal circuits where the circuit dimensions can be measured on the scale of yards instead of inches. However, compared with conventional printed circuit board circuits, the textile manufacturing process and the electrical/mechanical properties of the fibers used in making the textile place unusual constraints on the electrical performance of textile circuits. In the case of distributed sensors connected via an electronic fabric, signal attenuation and the ability to form reliable interconnections are major challenges. To explore these challenges we have woven and knitted a variety of electrical transmission lines and optical fibers in fabrics to analyze their performance. The formation of interconnects and disconnects between conductors woven in textiles is also discussed, and a passive acoustic array is described as a possible electronic textile application.

Microhardness Testing on Via Fill Material for Via In Pad Technology

2003 ◽  
Author(s):  
Norman J. Armendariz ◽  
Carolyn McCormick
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Strong Dependence ◽  
Circuit Board ◽  
Electrical Performance ◽  
Gravimetric Analysis ◽  
Passive Components ◽  
Root Cause ◽  
Fill Material ◽  
Signal Routing

Abstract Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.

Electrical Characterization of Low-Profile Copper Foil for Reduced Surface Roughness Loss

2016 ◽  
Vol 2016 (1) ◽  
pp. 000358-000363 ◽  
Author(s):  
Qianfei Su ◽  
A. Ege Engin ◽  
Jerry Aguirre
Keyword(s):  
Surface Roughness ◽  
Cross Sections ◽  
Transmission Lines ◽  
High Frequency ◽  
Printed Circuit Board ◽  
Electrical Characterization ◽  
Cavity Resonator ◽  
Circuit Board ◽  
Low Profile ◽  
Measure Surface Roughness

Abstract Signal attenuation in transmission lines is a major issue for reliable transmission in high frequency range. Knowledge of the electrical parameters of printed circuit board (PCB), including dielectric constant and loss tangent, is critical. Moreover, surface roughness has a great effect on loss in high frequency. This paper demonstrates an effective simulation fitting method for electrical material characterization. Cavity resonator is chosen as the circuit for characterization. A methodology is presented to measure surface roughness from cross sections, and compared with values extracted from resonator measurements. Several materials and copper foils treatments, including low-profile, are analyzed in this paper.

Two-Level Nonlinear Mixed Discrete-Continuous Optimization-Based Design: An Application to Printed Circuit Board Assemblies

1992 ◽  
Vol 114 (4) ◽  
pp. 425-435 ◽  
Author(s):  
S. Praharaj ◽  
S. Azarm
Keyword(s):  
Large Scale ◽  
Printed Circuit Board ◽  
Continuous Optimization ◽  
The Other ◽  
Circuit Board ◽  
Continuous Variables ◽  
Discrete Variables ◽  
Printed Circuit ◽  
Monotonicity Analysis ◽  
Optimization Based Design

In this paper, a new approach for optimization-based design of nonlinearly mixed discrete-continuous problems has been developed. The approach is based on a two-level decomposition strategy in which the entire domain of variables is partitioned into two levels, one involving the continuous variables and the other involving the discrete variables. Variables in one level are optimized for fixed values of the variable from the other level. A modified penalty function is formed, based on monotonicity analysis, to solve for the discrete variables, and a conventional optimization method is used to solve for the continuous variables. To improve the computational effectiveness of the approach, a constrained derivative relationship is also adopted. The performance of the entire algorithm is then demonstrated through an example involving a simplified model for printed circuit board assemblies. The objective in the example is to maximize assembly reliability by: (1) adding redundant components to the boards, and (2) optimally distributing allocated mass flow to the individual channels of the circuit boards. Number of variables in the example is then varied to investigate the effectiveness and potential of the approach for large-scale problems.

A Novel Discrete Passives Integration on Organic Substrate

2005 ◽  
Author(s):  
Vasudivan Sunappan ◽  
Chee Wai Lu ◽  
Lai Lai Wai ◽  
Wei Fan ◽  
Boon Keng Lok
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Board ◽  
Organic Substrate ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Electrical Performance ◽  
Core Material ◽  
Bottom Surface ◽  
Passive Components ◽  
Printed Circuit

A novel process has been developed to embed discrete (surface mountable) passive components like capacitors, resistors and inductors using printed circuit board fabrication technology. The process comprises of mounting passive components on top surface of a core PCB (printed circuit board) material using surface mount technology. The passive components mounting were designed in multiple clusters within the PCB. Dielectric sheets are sandwiched between top surface of core PCB and second PCB material for lamination process. A direct interconnection of the passive components to one or more integrated circuits (IC) is further accomplished by mounting the ICs on the bottom surface of the core material in an area directly under the passive components. The close proximity of the embedded passive components such as capacitors to an IC improved electrical performance by providing impedance reduction and resonance suppression at high frequency range. The reliability of solder joints was evaluatedd by temperature cycling test.

An Experimental Assessment of Numerical Predictive Accuracy for Electronic Component Heat Transfer in Forced Convection—Part II: Results and Discussion

2003 ◽  
Vol 125 (1) ◽  
pp. 76-83 ◽  
Author(s):  
Peter J. Rodgers ◽  
Vale´rie C. Eveloy ◽  
Mark R. Davies
Keyword(s):  
Heat Transfer ◽  
Forced Convection ◽  
Printed Circuit Board ◽  
Predictive Accuracy ◽  
Numerical Models ◽  
Circuit Board ◽  
Junction Temperature ◽  
Electrical Performance ◽  
Test Cases ◽  
Computational Fluid Dynamics Cfd

Numerical predictive accuracy is assessed for component-printed circuit board (PCB) heat transfer in forced convection using a widely used computational fluid dynamics (CFD) software. In Part I of this paper, the benchmark test cases, experimental methods and numerical models were described. Component junction temperature prediction accuracy for the populated board case is typically within ±5°C or ±10%, which would not be sufficient for temperature predictions to be used as boundary conditions for subsequent reliability and electrical performance analyses. Neither the laminar or turbulent flow model resolve the complete flow field, suggesting the need for a turbulence model capable of modeling transition. The full complexity of component thermal interaction is shown not to be fully captured.

Crosstalk Simulation Based on Full Wave S-Parameter Extraction Method between High-Speed Signals

2012 ◽  
Vol 433-440 ◽  
pp. 3514-3520
Author(s):  
Hong Tao Sun ◽  
Shu Guo Xie ◽  
Yan Liu ◽  
Bang Jun Chen
Keyword(s):  
Transmission Lines ◽  
High Speed ◽  
Printed Circuit Board ◽  
Simulation Method ◽  
Parameter Extraction ◽  
Circuit Board ◽  
Frequency Domain Method ◽  
Coupling Mechanism ◽  
Full Wave ◽  
S Parameter

Crosstalk between high speed parallel bus signals is one of the most important signal integrity(SI) issues. In this article, a crosstalk simulation method based on full-wave scattering parameters extraction for transmission lines is researched. First, the coupling mechanism between transmission lines is analyzed using S-Parameter network theory and a fast frequency-domain method for crosstalk calculation is introduced. Then based on this method, some basic rules of crosstalk are studied in details and the method is validated by simulation results which agree well with those of RLGC model. At the end of this paper, a practical crosstalk simulation example between high speed data bus signals on a 8-layered printed circuit board is demonstrated step by step.

Experimental and Numerical Investigation of the Reliability of Double-Sided Area Array Assemblies

2006 ◽  
Vol 128 (4) ◽  
pp. 441-448 ◽  
Author(s):  
S. Chaparala ◽  
J. M. Pitarresi ◽  
S. Parupalli ◽  
S. Mandepudi ◽  
M. Meilunas
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Mirror Image ◽  
Circuit Board ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Area Array ◽  
Plastic Ball

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.

Two-Level Nonlinear Mixed Discrete-Continuous Optimization-Based Design: An Application to Printed Circuit Board Assemblies

1992 ◽  
Author(s):  
S. Praharaj ◽  
Shapour Azarm
Keyword(s):  
Large Scale ◽  
Printed Circuit Board ◽  
Continuous Optimization ◽  
The Other ◽  
Circuit Board ◽  
Continuous Variables ◽  
Discrete Variables ◽  
Printed Circuit ◽  
Monotonicity Analysis ◽  
Optimization Based Design

Abstract In this paper, a new approach for optimization-based design of non-linearly mixed discrete-continuous problems has been developed. The approach is based on a two-level decomposition strategy in which the entire domain of variables is partitioned into two levels, one involving the continuous variables and the other involving the discrete variables. Variables in one level are optimized for fixed values of the variable from the other level. A modified penalty function is formed, based on monotonicity analysis, to solve for the discrete variables, and a conventional optimization method was used to solve for the continuous variables. To improve the computational effectiveness of the approach, a constrained derivative relationship was also adopted. The performance of the entire algorithm is then demonstrated through an example involving printed circuit board assemblies. The objective in the example is to maximize assembly reliability by: (1) adding redundant components to the boards and (2) optimally distributing allocated mass flow to the individual channels of the circuit boards. Number of variables in the example is then varied to investigate the effectiveness and potential of the approach for large-scale problems.

Session 1(b): Basic Techniques—Electronics: A Review of Postal Engineering Logic Units

1969 ◽  
Vol 184 (8) ◽  
pp. 41-51
Author(s):  
H. Goodison
Keyword(s):  
Large Scale ◽  
Printed Circuit Board ◽  
Design Method ◽  
Circuit Board ◽  
Actual Performance ◽  
Printed Circuit ◽  
Large Scale Integration ◽  
Current Assessment ◽  
Standard Set ◽  
Scale Integration

The paper describes why control elements using discrete components mounted on a printed circuit board were chosen for postal mechanization equipments. Basic design considerations are listed, and principles determining the choice of components stated. The decision to provide both ‘nor’ and ‘not-and’ elements is explained, and the reasons given why negative logic is used. With the use of B.S. symbols it is shown how logic diagrams can easily be converted to functional diagrams. A brief description of each logic unit in the standard set is given and the set of peripheral units listed. Mention is made of the design method and the emphasis placed on noise immunity. Constructional techniques and the use of an automatic tester are described. Current assessment of the actual performance of the units is given and future possibilities, including large-scale integration and M.O.S.T. devices, are discussed.

scholarly journals Novel Low-Cost Power Divider for 5.8 GHz

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 699
Author(s):  
Tso-Jung Chang ◽  
Krishna Pande ◽  
Heng-Tung Hsu
Keyword(s):  
Transmission Lines ◽  
Insertion Loss ◽  
Printed Circuit Board ◽  
Characteristic Impedance ◽  
Past Research ◽  
Size Reduction ◽  
Circuit Board ◽  
Superior Performance ◽  
Published Data ◽  
Coupled Line

This paper presents a new capacitive lump-free structure for power dividers using a printed-circuit board, while maintaining size reduction and physical isolation. The conventional lumped capacitors approach has self-resonant problem and cause worse S 22 and isolation at high frequencies. To overcome such technical issues, the coupled-line structures were introduced in the isolation network. After optimizing the distance between output ports and position of the isolation network, tuning the characteristic impedance and electrical length of transmission lines can decide the value of the lump resistor. The first example was designed at 1 GHz, and the resistor in the isolation network was 330 ohm, having 0.2-dB insertion loss and 19% total bandwidth, while maintaining 80-degree distance between split ports and 180-degree total length, providing 21% to 67% size reduction. The second example was designed at 5.8 GHz, which was five times greater than in past research, using an RO4003C substrate while maintaining a 0.24-dB insertion loss, 17% total bandwidth, and 0.06 dB amplitude imbalance, which was only 0.01 dB more than in recent research. Such superior performance is mainly attributed to the coupled transmission lines in the isolation network featuring a capacitive lump-free isolation network. Our data indicate that amplitude imbalance, bandwidth, and miniaturization are superior to any published data.

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