Electrical Characterization of Low-Profile Copper Foil for Reduced Surface Roughness Loss

2016 ◽  
Vol 2016 (1) ◽  
pp. 000358-000363 ◽  
Author(s):  
Qianfei Su ◽  
A. Ege Engin ◽  
Jerry Aguirre
Keyword(s):  
Surface Roughness ◽  
Cross Sections ◽  
Transmission Lines ◽  
High Frequency ◽  
Printed Circuit Board ◽  
Electrical Characterization ◽  
Cavity Resonator ◽  
Circuit Board ◽  
Low Profile ◽  
Measure Surface Roughness

Abstract Signal attenuation in transmission lines is a major issue for reliable transmission in high frequency range. Knowledge of the electrical parameters of printed circuit board (PCB), including dielectric constant and loss tangent, is critical. Moreover, surface roughness has a great effect on loss in high frequency. This paper demonstrates an effective simulation fitting method for electrical material characterization. Cavity resonator is chosen as the circuit for characterization. A methodology is presented to measure surface roughness from cross sections, and compared with values extracted from resonator measurements. Several materials and copper foils treatments, including low-profile, are analyzed in this paper.

scholarly journals Transition from Microstrip Line to Ridge Empty Substrate Integrated Waveguide Based on the Equations of the Superellipse

2020 ◽  
Vol 10 (22) ◽  
pp. 8101
Author(s):  
David Herraiz ◽  
Héctor Esteban ◽  
Juan A. Martínez ◽  
Angel Belenguer ◽  
Santiago Cogollos ◽  
...  
Keyword(s):  
Transmission Lines ◽  
Microstrip Line ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Substrate Integrated Waveguide ◽  
Fractional Bandwidth ◽  
Low Profile ◽  
Metal Layers ◽  
Planar Transmission Lines ◽  
Wideband Transition

In recent years, multiple technologies have been proposed with the aim of combining the characteristics of traditional planar and non-planar transmission lines. The first and most popular of these technologies is the Substrate Integrated Waveguide (SIW), where rows of metallic vias are mechanized in a printed circuit board (PCB). These vias, together with the top and bottom metal layers of the PCB, form a channel for the propagation of the electromagnetic fields, similar to that of a rectangular waveguide, but through a dielectric body, which increases the losses. To reduce these losses, the empty substrate integrated waveguide (ESIW) was recently proposed. In the ESIW, the dielectric is removed from the substrate, and this results in better performance (low profile and easy manufacturing as in SIW, but lower losses and better quality factor for resonators). Recently, to increase the operational bandwidth (monomode propagation) of the ESIW, the ridge ESIW (RESIW) and a transition from RESIW to microstrip line was proposed. In this work, a new and improved wideband transition from microstrip line (MS) to RESIW, with a dielectric taper based on the equations of the superellipse, is proposed. The new wideband transition presents simulated return losses in a back-to-back transition greater than 20 dB in an 87% fractional bandwidth, while in the previous transition the fractional bandwidth was 82%. This is an increment of 5%. In addition, the transition presents simulated return losses greater than 26 dB in an 84% fractional bandwidth. For validation purposes, a back-to-back configuration of the new transition was successfully manufactured and measured. The measured return loss is better than 14 dB with an insertion loss lower than 1 dB over the whole band.

scholarly journals Characterization of Wire-Bonding on LDS Materials and HF-PCBs for High-Frequency Applications

2022 ◽  
Vol 6 (1) ◽  
pp. 9
Author(s):  
Thomas Guenther ◽  
Kai Werum ◽  
Ernst Müller ◽  
Marius Wolf ◽  
André Zimmermann
Keyword(s):  
Surface Roughness ◽  
High Frequency ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Wire Bonding ◽  
Circuit Board ◽  
Quality Characteristic ◽  
Bond Quality ◽  
Wire Bonds ◽  
Pull Tests

Thermosonic wire bonding is a well-established process. However, when working on advanced substrate materials and the associated required metallization processes to realize innovative applications, multiple factors impede the straightforward utilization of the known process. Most prominently, the surface roughness was investigated regarding bond quality in the past. The practical application of wire bonding on difficult-to-bond substrates showed inhomogeneous results regarding this quality characteristic. This study describes investigations on the correlation among the surface roughness, profile peak density and bonding quality of Au wire bonds on thermoplastic and thermoset-based substrates used for high-frequency (HF) applications and other high-end applications. FR4 PCB (printed circuit board flame resitant class 4) were used as references and compared to HF-PCBs based on thermoset substrates with glass fabric and ceramic filler as well as technical thermoplastic materials qualified for laser direct structuring (LDS), namely LCP (liquid crystal polymer), PEEK (polyether ether ketone) and PTFE (polytetrafluoroethylene). These LDS materials for HF applications were metallized using autocatalytic metal deposition to enable three-dimensional structuring, eventually. For that purpose, bond parameters were investigated on the mentioned test substrates and compared with state-of-the-art wire bonding on FR4 substrates as used for HF applications. Due to the challenges of the limited thermal conductivity and softening of such materials under thermal load, the surface temperatures were matched up by thermography and the adaptation of thermal input. Pull tests were carried out to determine the bond quality with regard to surface roughness. Furthermore, strategies to increase reliability by the stitch-on-ball method were successfully applied.

scholarly journals Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

Energies ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1495
Author(s):  
Loris Pace ◽  
Nadir Idir ◽  
Thierry Duquesne ◽  
Jean-Claude De Jaeger
Keyword(s):  
High Frequency ◽  
Printed Circuit Board ◽  
Power Converters ◽  
Calibration Procedure ◽  
Circuit Board ◽  
Design System ◽  
Switching Speed ◽  
Parasitic Inductance ◽  
Frequency Converters ◽  
S Parameters

Due to the high switching speed of Gallium Nitride (GaN) transistors, parasitic inductances have significant impacts on power losses and electromagnetic interferences (EMI) in GaN-based power converters. Thus, the proper design of high-frequency converters in a simulation tool requires accurate electromagnetic (EM) modeling of the commutation loops. This work proposes an EM modeling of the parasitic inductance of a GaN-based commutation cell on a printed circuit board (PCB) using Advanced Design System (ADS®) software. Two different PCB designs of the commutation loop, lateral (single-sided) and vertical (double-sided) are characterized in terms of parasitic inductance contribution. An experimental approach based on S-parameters, the Cold FET technique and a specific calibration procedure is developed to obtain reference values for comparison with the proposed models. First, lateral and vertical PCB loop inductances are extracted. Then, the whole commutation loop inductances including the packaging of the GaN transistors are determined by developing an EM model of the device’s internal parasitic. The switching waveforms of the GaN transistors in a 1 MHz DC/DC converter are given for the different commutation loop designs. Finally, a discussion is proposed on the presented results and the development of advanced tools for high-frequency GaN-based power electronics design.

scholarly journals Highly Compact Through-Wire Microstrip to Empty Substrate Integrated Coaxial Line Transition

2021 ◽  
Vol 11 (15) ◽  
pp. 6885
Author(s):  
Marcos D. Fernandez ◽  
José A. Ballesteros ◽  
Angel Belenguer
Keyword(s):  
Printed Circuit Board ◽  
Low Cost ◽  
Coaxial Line ◽  
Circuit Board ◽  
Central Layer ◽  
Printed Circuit ◽  
Integrated Technology ◽  
Low Profile ◽  
The Many ◽  
High Degree

Empty substrate integrated coaxial line (ESICL) technology preserves the many advantages of the substrate integrated technology waveguides, such as low cost, low profile, or integration in a printed circuit board (PCB); in addition, ESICL is non-dispersive and has low radiation. To date, only two transitions have been proposed in the literature that connect the ESICL to classical planar lines such as grounded coplanar and microstrip. In both transitions, the feeding planar lines and the ESICL are built in the same substrate layer and they are based on transformed structures in the planar line, which must be in the central layer of the ESICL. These transitions also combine a lot of metallized and non-metallized parts, which increases the complexity of the manufacturing process. In this work, a new through-wire microstrip-to-ESICL transition is proposed. The feeding lines and the ESICL are implemented in different layers, so that the height of the ESICL can be independently chosen. In addition, it is a highly compact transition that does not require a transformer and can be freely rotated in its plane. This simplicity provides a high degree of versatility in the design phase, where there are only four variables that control the performance of the transition.

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

2002 ◽  
Vol 124 (3) ◽  
pp. 205-211 ◽  
Author(s):  
John H. Lau ◽  
S. W. Ricky Lee ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Test Results ◽  
Pcb Assembly ◽  
Creep Analysis ◽  
Chip Scale Package ◽  
Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

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