Relaxed Silicon-Germanium on Insulator (SGOI)

2001 ◽  
Vol 686 ◽  
Author(s):  
Zhiyuan Cheng ◽  
Matthew T. Currie ◽  
Chris W. Leitz ◽  
Gianni Taraschi ◽  
Minjoo L. Lee ◽  
...  

AbstractWe have fabricated high quality SGOI substrates and demonstrated high mobility enhancement in strained-Si MOSFET's fabricated on the relaxed SGOI substrates with a Ge content of 25%. The substrates were fabricated by wafer bonding. The initial relaxed Si1−xGex layers were grown on Si donor substrates by a graded epitaxial growth technology using ultrahigh vacuum chemical vapor deposition (UHVCVD). The SiGe wafers were then bonded to oxidized silicon handle wafers. Two different approaches have been developed to fabricate SGOI substrates: an etch-back process utilizing a 20% Ge layer as a natural etch stop, and a hydrogen-induced wafer delamination process using H+ implantion. The resultant SiGe film quality was compared among the different approaches. Large-area strained-Si MOSFET's were then fabricated on the SGOI substrates. Epitaxial regrowth was used to produce the upper portion of the relaxed SiGe and the surface strained Si layer. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFET's. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si1−xGex layer.

2020 ◽  
Vol 10 (19) ◽  
pp. 6656
Author(s):  
Stefano Lai ◽  
Giulia Casula ◽  
Pier Carlo Ricci ◽  
Piero Cosseddu ◽  
Annalisa Bonfiglio

The development of electronic devices with enhanced properties of transparency and conformability is of high interest for the development of novel applications in the field of bioelectronics and biomedical sensing. Here, a fabrication process for all organic Organic Field-Effect Transistors (OFETs) by means of large-area, cost-effective techniques such as inkjet printing and chemical vapor deposition is reported. The fabricated device can operate at low voltages (as high as 4 V) with ideal electronic characteristics, including low threshold voltage, relatively high mobility and low subthreshold voltages. The employment of organic materials such as Parylene C, PEDOT:PSS and 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS pentacene) helps to obtain highly transparent transistors, with a relative transmittance exceeding 80%. Interestingly enough, the proposed process can be reliably employed for OFET fabrication over different kind of substrates, ranging from transparent, flexible but relatively thick polyethylene terephthalate (PET) substrates to transparent, 700-nm-thick, compliant Parylene C films. OFETs fabricated on such sub-micrometrical substrates maintain their functionality after being transferred onto complex surfaces, such as human skin and wearable items. To this aim, the electrical and electromechanical stability of proposed devices will be discussed.


ACS Nano ◽  
2011 ◽  
Vol 5 (9) ◽  
pp. 7198-7204 ◽  
Author(s):  
Michael E. Ramón ◽  
Aparna Gupta ◽  
Chris Corbet ◽  
Domingo A. Ferrer ◽  
Hema C. P. Movva ◽  
...  

2017 ◽  
Vol 2017 (1) ◽  
pp. 000569-000575 ◽  
Author(s):  
André Cardoso ◽  
Raquel Pinto ◽  
Elisabete Fernandes ◽  
Steffen Kroehnert

Abstract Due to its versatility for high density, heterogeneous integration, Wafer Level Fan Out (WLFO) packaging has recently seen a tremendous growth in a broad array of applications, from telecommunications and automotive, to optical and environmental sensing, while addressing the challenges of the next big wave of the Internet of Things (IoT). In this context, WLFO is continuously being challenged to include new families of MEMS/NEMS/MOEMS sensors, low thermal budget devices and biochips with microfluidics for biomedical applications. Recent developments in WLFO technology by NANIUM [1] demonstrated the implementation of a keep-out-zone (KOZ) mechanism intended to 1st) protect sensitive sensor areas during the backend processing of WLFO wafers and 2nd) create open zones on the Re-Distribution Layers (RDL). This way, the KOZ mechanism provides a physical, direct path from the embedded device to the environment. This is a necessary feature for environment sensing (e.g., pressure) or to create optical paths free of dielectric and protected from the harsh chemistry steps of the WLFO process. This paper describes new developments on KOZ, implemented with SU-8 photoresist as a WLFO dielectric, whose application is a novelty in the WLFO platform. The use of SU-8 and the KOZ with it, addresses some gaps of the current WLFO technology towards the integration of chips with bio-sensitive areas and sensors with low thermal budget. Due to its well-known bio-compatibility and inert behavior, SU-8 can be used as a neutral dielectric to be in direct contact to target fluids (e.g., sera, blood). Also, due to its low curing temperature, SU-8 allows a very low temperature WLFO process and thus the embedding of temperature-limited devices that have been outside the WLFO realm, for example, magneto-resistive or magnetic-spin sensor chips, which degrades its performance above 160°C. More interestingly, SU-8 exhibits a particular non-conformal behavior, which creates very smooth surfaces even over the mildly rough mold compound area of a fan-out package. Adding to this, SU-8 is readily available in the market in a wide range of thicknesses, spanning from 0.5 μm to >100 μm, and further allowing multiple spin coatings to build thick layers. Thus, SU-8 can provide smooth and deep enough channels for microfluidic flow over the chip sensing areas and, at the same time, provide the necessary layer thickness discrimination for the KOZ mechanism. Combining these features, the SU-8 layers in WLFO can play the triple role of 1) RDL dielectric insulation, 2) KOZ mechanism and 3) embedded microfluidic channels as part of the RDL. In summary, besides the unprecedented use of SU-8 in WLFO packaging, KOZ implementation on SU-8 provides a true, attainable bridge between WLFO and integrated microfluidic applications, for biosensing and biomedical applications in general. Outlooking the potentialities of such a merge, a Fan-Out package can embed several chips interconnected by RDL lines, as it currently allows, and also connected by microfluidic channel for multi-point, multi-function biosensing, constituting a true Lab-on-Package, cost-effective solution. Instead of building all sensing areas and microfluidic channels over a large silicon (Si) chip, this solution builds the feed-in, feed-out areas of the microfluidic channel over the inexpensive fan-out area, minimizing the sensing chip area, with the consequent front-end cost reduction.


2012 ◽  
Vol 1400 ◽  
Author(s):  
Ranajit Sai ◽  
Suresh D. Kulkarni ◽  
K. J. Vinoy ◽  
Navakanta Bhat ◽  
S. A. Shivashankar

ABSTRACTFurther miniaturization of magnetic and electronic devices demands thin films of advanced nanomaterials with unique properties. Spinel ferrites have been studied extensively owing to their interesting magnetic and electrical properties coupled with stability against oxidation. Being an important ferrospinel, zinc ferrite has wide applications in the biological (MRI) and electronics (RF-CMOS) arenas. The performance of an oxide like ZnFe2O4depends on stoichiometry (defect structure), and technological applications require thin films of high density, low porosity and controlled microstructure, which depend on the preparation process. While there are many methods for the synthesis of polycrystalline ZnFe2O4powder, few methods exist for the deposition of its thin films, where prolonged processing at elevated temperature is not required. We report a novel, microwave-assisted, low temperature (<100°C) deposition process that is conducted in the liquid medium, developed for obtaining high quality, polycrystalline ZnFe2O4thin films on technologically important substrates like Si(100). An environment-friendly solvent (ethanol) and non-hazardous oxide precursors (β-diketonates of Zn and Fe in 1:2 molar ratio), forming a solution together, is subjected to irradiation in a domestic microwave oven (2.45 GHz) for a few minutes, leading to reactions which result in the deposition of ZnFe2O4films on Si (100) substrates suspended in the solution. Selected surfactants added to the reactant solution in optimum concentration can be used to control film microstructure. The nominal temperature of the irradiated solution, i.e., film deposition temperature, seldom exceeds 100°C, thus sharply lowering the thermal budget. Surface roughness and uniformity of large area depositions (50x50 mm2) are controlled by tweaking the concentration of the mother solution. Thickness of the films thus grown on Si (100) within 5 min of microwave irradiation can be as high as several microns. The present process, not requiring a vacuum system, carries a very low thermal budget and, together with a proper choice of solvents, is compatible with CMOS integration. This novel solution-based process for depositing highly resistive, adherent, smooth ferrimagnetic films on Si (100) is promising to RF engineers for the fabrication of passive circuit components. It is readily extended to a wide variety of functional oxide films.


Author(s):  
Kaito Kanahashi ◽  
Masatou Ishihara ◽  
Masataka Hasegawa ◽  
Hiromichi Ohta ◽  
Taishi Takenobu

Abstract This study reports on the thermoelectric properties of large-area graphene films grown by chemical vapor deposition (CVD) methods. Using the electric double layer gating technique, both the continuous doping of hole or electron carriers and modulation of the Fermi energy are achieved, leading to wide-range control of the Seebeck coefficient and electrical conductivity. Consequently, the maximum power factors of the CVD-grown large-area graphene films are 6.93 and 3.29 mW m–1 K–2 for p- and n-type carrier doping, respectively. These results are the best values among large-scale flexible materials, such as organic conducting polymers and carbon nanotubes, suggesting that CVD-grown large-area graphene films have potential for thermoelectric applications.


2002 ◽  
Vol 745 ◽  
Author(s):  
Stefan Harasek ◽  
Heinz D. Wanzenboeck ◽  
Helmut Langfischer ◽  
Emmerich Bertagnolli

ABSTRACTWe report on metal-organic chemical vapor deposition (MOCVD) of ultrathin zirconium dioxide on (100) silicon. Special emphasis is put on the evolution of surface topography and the impact of processing parameters on the chemical composition of the films. Electrical characterization by means of MOS structures has been performed to assess the interface quality and the dielectric properties of the layers. Interface trap density is observed to be around 5.1011 cm-2.eV-1 at midgap for (100)-oriented substrates. Leakage currents in the ultrathin regime are significantly reduced compared to equivalent SiO2-layers. Trap density and leakage current are strongly sensitive to annealing in different atmospheres. However, electrical characteristics are shown to be positively affected rather by annealing in slightly reducing than in oxidizing atmospheres. All temperatures throughout the gate insulator formation process do not need to exceed 650°C, and thus allow to keep the thermal budget low.


1994 ◽  
Vol 340 ◽  
Author(s):  
M. McKee ◽  
G.S. Tompa ◽  
P.A. Zawadzki ◽  
A. Thompson ◽  
A. Gurary ◽  
...  

ABSTRACTCompound semiconductors are at the heart of todays advanced digital and optoelectronic devices. As device production levels increase, so too does the need for high throughput deposition systems. The vertical rotating disk reactor (RDR) has been scaled to dimensions allowing metal organic chemical vapor deposition (MOCVD) on multiple substrates located on a 300 mm diameter platter. This symetric large area reactor affords easy access over a wide range of angles for optical monitoring and control of the growth process. The RDR can be numerically modeled in a straightforward manner, and we have derived scaling rules allowing the prediction of optimum process conditions for larger reactor sizes. The material results give excellent agreement with the modeling, demonstrating GaAs/AlAs structures with <±0.9% thickness uniformities on up to 17-50mm or 4-100mm GaAs substrates. Process issues related to reactor scaling are reviewed. With high reactant efficiencies and short cycle times between growths, through the use of a vacuum loadlock, the costs per wafer are found to be dramatically less than in alternative process reactors. The high reactant utilization, in combination with a dedicated and highly efficient exhaust scrubbing system, minimizes the systems environmental impact.


Sign in / Sign up

Export Citation Format

Share Document