Crystallographic Texture Characterization of Inlaid Copper Interconnects

2001 ◽  
Vol 672 ◽  
Author(s):  
Inka Zienert ◽  
Paul Besser ◽  
Werner Blum ◽  
Ehrenfried Zschech
Keyword(s):  
Integrated Circuits ◽  
Diffusion Path ◽  
Copper Interconnects ◽  
Fast Diffusion ◽  
High Angle ◽  
Current Densities ◽  
Interconnect Lines ◽  
Texture Characterization ◽  
Interconnect System

Developing faster integrated circuits places incredible demands on the interconnect system. The smaller feature sizes lead to excessive current densities, which in turn make the interconnect lines more susceptible to electromigration (EM) failure.[1] Studies have shown that EM performance can be improved by increasing the strength of the {111} texture in conventionally- fabricated aluminum-based lines.[2-6] The strong {111} texture minimizes the presence of high- angle grain boundaries along the interconnect line, thus minimizing a fast-diffusion path for EM mass transport.[2-4,7-12]

The Effect of Cluster Interactions on Electromigration Induced Stress Evolution in Confined Metal Lines

1995 ◽  
Vol 391 ◽  
Author(s):  
D.D. Brown ◽  
J.E. Sanchez ◽  
P.R. Besser ◽  
M.A. Korhonen ◽  
C.-Y. Li
Keyword(s):  
Integrated Circuits ◽  
Grain Boundaries ◽  
Length Distribution ◽  
Diffusion Path ◽  
Line Length ◽  
Segment Length ◽  
Stress Profile ◽  
Fast Diffusion ◽  
Metal Interconnects ◽  
Interconnect Lines

AbstractIn near-bamboo interconnect lines used in advanced integrated circuits, electromigration flux divergences occur at the intersection between polycrystalline cluster segments (where grain boundaries offer a fast diffusion path), and bamboo segments (where there are no grain boundaries along the line length). For confined, passivated metal interconnects, these flux divergences are linked to the evolution of significant mechanical stresses in the metal. A quasisteady state stress distribution builds up relatively quickly in the cluster segments and remains unchanged until there is significant diffusion into the bamboo segments. The stress profile of a given cluster then becomes dependent on neighboring clusters as well as the diffusivity and flux in the separating bamboo segments. Previous analyses of electromigration failure in interconnect lines have focused on the distribution of cluster lengths and the stress build up in isolated cluster segments. In this paper, we show that the bamboo length distribution can strongly affect the interaction between clusters and the evolution of stresses in a near-bamboo interconnect during electromigration. We present simulation results, using a ratio of cluster to bamboo diffusivity Dc/Db=100, which show greater interactions and larger maximum stresses in cluster segments as the average bamboo segment length decreases and as the bamboo segment length distribution widens.

Electromigration Characterization of Damascene Copper Interconnects: Comparison Between CVD Copper and ECD Copper.

2001 ◽  
Vol 714 ◽  
Author(s):  
Thierry Berger ◽  
Lucile Arnaud ◽  
Gérard Tartavel ◽  
Gérard Lormand
Keyword(s):  
Seed Layer ◽  
Chemical Vapor ◽  
Diffusion Path ◽  
Point Of View ◽  
Copper Interconnects ◽  
Strong Impact ◽  
Wafer Level ◽  
Accelerated Lifetime ◽  
Damascene Interconnects

ABSTRACTWe have characterized the electromigration performance of copper damascene interconnects using moderately and highly accelerated lifetime tests respectively at package and wafer level. Two metallizations have been studied: Chemical Vapor Deposition (CVD) copper deposited on CVD TiN (Process A) and electroplated (ECD) copper deposited on CVD TiN using 90 nm of CVD copper as a seed-layer (Process B). All metallizations were passivated with SiO2. Two line widths have been characterized: 0.6μm and 4μm.For wide lines, we obtained similar activation energies (Ea) for both metallizations (0.63 for process A and 0.65 eV for process B). For narrow lines, the Ea value is 0.8eV for CVD copper whereas it is higher than 1eV for ECD copper. For wide lines of both metallizations, failure analysis performed with a Scanning Electron Microscope (SEM) gave clear evidences that microstructural gradients have a strong impact on voids and extrusions formation (i.e. that grain boundaries are an active diffusion path in spite of low Ea values). For narrow lines, diffusion at the upper interface is believed to be the main diffusion path.From the reliability point of view, the extrapolated lifetimes of the metallization including ECD copper are much higher (1 to 2 orders of magnitude depending on the line width) than for CVD copper.

Some applications of electron beam microanalysis techniques in VLSI process evaluation

1983 ◽  
Vol 41 ◽  
pp. 160-161
Author(s):  
Simon Thomas
Keyword(s):  
Integrated Circuits ◽  
Process Evaluation ◽  
Large Scale ◽  
Technology Development ◽  
Analytical Techniques ◽  
Successful Implementation ◽  
Analysis Of Failures ◽  
Characterization Of Materials ◽  
Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

Analytical electron microscopy of grain boundaries in Al-Cu metallizations

1992 ◽  
Vol 50 (2) ◽  
pp. 1684-1685
Author(s):  
J. R. Michael ◽  
A. D. Romig ◽  
D. R. Frear
Keyword(s):  
Electron Microscopy ◽  
Integrated Circuits ◽  
Failure Mode ◽  
Current Density ◽  
Thermal History ◽  
Analytical Electron Microscopy ◽  
Cu Metallization ◽  
Analytical Electron ◽  
Interconnect Lines

Al with additions of Cu is commonly used as the conductor metallizations for integrated circuits, the Cu being added since it improves resistance to electromigration failure. As linewidths decrease to submicrometer dimensions, the current density carried by the interconnect increases dramatically and the probability of electromigration failure increases. To increase the robustness of the interconnect lines to this failure mode, an understanding of the mechanism by which Cu improves resistance to electromigration is needed. A number of theories have been proposed to account for role of Cu on electromigration behavior and many of the theories are dependent of the elemental Cu distribution in the interconnect line. However, there is an incomplete understanding of the distribution of Cu within the Al interconnect as a function of thermal history. In order to understand the role of Cu in reducing electromigration failures better, it is important to characterize the Cu distribution within the microstructure of the Al-Cu metallization.

TEM characterization of WSix films

1994 ◽  
Vol 52 ◽  
pp. 848-849
Author(s):  
V. C. Kannan ◽  
S. M. Merchant ◽  
R. B. Irwin ◽  
A. K. Nanda ◽  
M. Sundahl ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Vapor Deposition ◽  
High Purity ◽  
Physical Vapor Deposition ◽  
Thermal Treatments ◽  
Rapid Thermal Anneal ◽  
Tungsten Silicide ◽  
Tem Characterization ◽  
Metal Silicides

Metal silicides such as WSi2, MoSi2, TiSi2, TaSi2 and CoSi2 have received wide attention in recent years for semiconductor applications in integrated circuits. In this study, we describe the microstructures of WSix films deposited on SiO2 (oxide) and polysilicon (poly) surfaces on Si wafers afterdeposition and rapid thermal anneal (RTA) at several temperatures. The stoichiometry of WSix films was confirmed by Rutherford Backscattering Spectroscopy (RBS). A correlation between the observed microstructure and measured sheet resistance of the films was also obtained.WSix films were deposited by physical vapor deposition (PVD) using magnetron sputteringin a Varian 3180. A high purity tungsten silicide target with a Si:W ratio of 2.85 was used. Films deposited on oxide or poly substrates gave rise to a Si:W ratio of 2.65 as observed by RBS. To simulatethe thermal treatments of subsequent processing procedures, wafers with tungsten silicide films were subjected to RTA (AG Associates Heatpulse 4108) in a N2 ambient for 60 seconds at temperatures ranging from 700° to 1000°C.

Micromechanics Measurements Applied to Integrated Circuit Microelectronics

1997 ◽  
Vol 473 ◽  
Author(s):  
David R. Clarke
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Fracture Resistance ◽  
Interface Fracture ◽  
New Techniques ◽  
Fracture Properties ◽  
Engineered Structures ◽  
Mechanical And Fracture Properties ◽  
Interconnect Lines ◽  
Metallic Interconnect

ABSTRACTAs in other engineered structures, fracture occasionally occurs in integrated microelectronic circuits. Fracture can take a number of forms including voiding of metallic interconnect lines, decohesion of interfaces, and stress-induced microcracking of thin films. The characteristic feature that distinguishes such fracture phenomena from similar behaviors in other engineered structures is the length scales involved, typically micron and sub-micron. This length scale necessitates new techniques for measuring mechanical and fracture properties. In this work, we describe non-contact optical techniques for probing strains and a microscopic “decohesion” test for measuring interface fracture resistance in integrated circuits.

Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages

2008 ◽  
Author(s):  
P. Schwindenhammer ◽  
H. Murray ◽  
P. Descamps ◽  
P. Poirier
Keyword(s):  
Laser Ablation ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Ablation Process ◽  
Thermally Induced ◽  
Electrical Failure ◽  
Electrical Phenomenon ◽  
Semiconductor Packages ◽  
Complex Semiconductor

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

Characterization of Interconnect Defects Using Scanning Thermal Conductivity Microscopy

2004 ◽  
Author(s):  
H.W. Ho ◽  
J.C.H. Phang ◽  
A. Altes ◽  
L.J. Balk
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
Large Scale

Abstract In this paper, scanning thermal conductivity microscopy is used to characterize interconnect defects due to electromigration. Similar features are observed both in the temperature and thermal conductivity micrographs. The key advantage of the thermal conductivity mode is that specimen bias is not required. This is an important advantage for the characterization of defects in large scale integrated circuits. The thermal conductivity micrographs of extrusion, exposed and subsurface voids are presented and compared with the corresponding topography and temperature micrographs.

Emerging Techniques for the Characterization of Nano-Mechanical Properties of Integrated Circuit Components

2008 ◽  
Author(s):  
Nicholas Randall ◽  
Rahul Premachandran Nair
Keyword(s):  
Mechanical Properties ◽  
Quality Control ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Manufacturing Process ◽  
Solder Bumps ◽  
Initial Work ◽  
Circuit Components ◽  
Materials Used

Abstract With the growing complexity of integrated circuits (IC) comes the issue of quality control during the manufacturing process. In order to avoid late realization of design flaws which could be very expensive, the characterization of the mechanical properties of the IC components needs to be carried out in a more efficient and standardized manner. The effects of changes in the manufacturing process and materials used on the functioning and reliability of the final device also need to be addressed. Initial work on accurately determining several key mechanical properties of bonding pads, solder bumps and coatings using a combination of different methods and equipment has been summarized.

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