Structural Characterization Of Sic Epitaxial Layers Grown On Porous Sic Substrates

2000 ◽  
Vol 640 ◽  
Author(s):  
S. E. Saddow ◽  
G. Melnychuk ◽  
M. Mynbaeva ◽  
I. Nikitina ◽  
W. M. Vetter ◽  
...  
Keyword(s):  
Dislocation Density ◽  
Epitaxial Layer ◽  
Preliminary Investigation ◽  
Analytical Techniques ◽  
Epitaxial Layers ◽  
Cross Sectional ◽  
Initial Substrate ◽  
Order Of Magnitude ◽  
Porous Sic

ABSTRACTA layer of porous SiC was fabricated by surface anodization of commercial 4H and 6H-SiC (0001)Si face off-axis wafers. A 8.5 μm 4H–SiC epilayer was grown on porous SiC (PSC) substrates using atmospheric pressure CVD. TEM investigation on cross-sectional specimens of the CVD epitaxial layers revealed that the presence of pores in the substrate does not lead to the formation of any micropipe in the epitaxial layer. The investigation also failed to detect a more than usual dislocation density on the basal plane of the epitaxial layer. Based upon the results of various analytical techniques applied to the CVD deposit we propose that the density of screw dislocations in the epitaxial layer is less than 5–104 cm−3. It should be noted that the density of similar types of dislocations in the initial substrate as determined by the TEM was ∼106 cm−3, so this preliminary investigation indicates that the epitaxial layer grown on PSC may have a reduction in dislocation density of more than an order of magnitude over those grown on conventional SiC substrates that are not porous. Synchrotron white beam x-ray topography (SWBXT) was performed on these layers. Comparison between the dislocation density on the porous and standard epitaxial layers proved to be very similar using this technique.

Comparison of Ion-Milling Techniques For Cross-Sectional TEM of Semiconductors

1985 ◽  
Vol 43 ◽  
pp. 166-167
Author(s):  
Julia T. Luck ◽  
C. W. Boggs ◽  
S. J. Pennycook
Keyword(s):  
Analytical Techniques ◽  
Sample Surface ◽  
Ion Milling ◽  
Cross Sectional ◽  
Reliable Technique ◽  
Near Surface ◽  
Transmission Electron ◽  
Thin Region ◽  
Transient Thermal

The use of cross-sectional Transmission Electron Microscopy (TEM) has become invaluable for the characterization of the near-surface regions of semiconductors following ion-implantation and/or transient thermal processing. A fast and reliable technique is required which produces a large thin region while preserving the original sample surface. New analytical techniques, particularly the direct imaging of dopant distributions, also require good thickness uniformity. Two methods of ion milling are commonly used, and are compared below. The older method involves milling with a single gun from each side in turn, whereas a newer method uses two guns to mill from both sides simultaneously.

Epitaxial growth and characterization of BP on Si(100) substrate for use in c-GaN study

2005 ◽  
Vol 891 ◽  
Author(s):  
Tomohiko Takeuchi ◽  
Suzuka Nishimura ◽  
Tomoyuki Sakuma ◽  
Satoru Matumoto ◽  
Kazutaka Terashima
Keyword(s):  
Epitaxial Layer ◽  
Careful Analysis ◽  
X Ray Diffraction ◽  
Si Substrate ◽  
Cross Sectional ◽  
X Ray ◽  
Si Substrates ◽  
Impurity Doping ◽  
Hall Effect Measurements

ABSTRACTBoronmonophosphide(BP) is one of the suitable materials for a buffer layer between the c-GaN(100) and Si(100) substrates. The growth of BP layer was carried out by MOCVD on Si(100) substrate of 2 inch in diameter. The growth rate was over 2 μm/h without any troubles such as the bowing or cracking. In addition, the thickness of BP epitaxial layer was uniform over a wide area. A careful analysis of x-ray diffraction suggested that the growth of BP epitaxial layer inherited the crystal orientation from Si(100) substrate. Cross-sectional TEM images showed some defects like dislocations near the interface between BP layer and Si substrate. The Hall effect measurements indicated that the conduction type of BP films grown on the both n-Si and p-Si substrates was n-type without impurity doping, and that the mobility and carrier concentrations were typically 357cm2/Vs and 1.5×1020cm−3(on n-Si) and 63cm2/Vs and 1.9×1019cm−3(on p-Si), respectively. In addition, c-GaN was grown on the substrate of BP/Si(100) by RF-MBE.

Characterization of Porous SiC Substrates and of the Epilayer Structures Grown on Them

2002 ◽  
Vol 742 ◽  
Author(s):  
Balaji Raghothamachar ◽  
Jie Bai ◽  
William M. Vetter ◽  
Perena Gouma ◽  
Michael Dudley ◽  
...  
Keyword(s):  
Dislocation Density ◽  
Optical Microscopy ◽  
Epitaxial Growth ◽  
Screw Dislocation ◽  
Pore Morphology ◽  
Porous Substrate ◽  
X Ray ◽  
Porous Sic ◽  
Screw Dislocation Density

ABSTRACTPorous 6H-SiC and 4H-SiC wafers formed by anodization have been characterized in this study prior to and following the CVD deposition of SiC epitaxial layers, using a combination of synchrotron white beam x-ray topography (SWBXT), SEM, TEM and optical microscopy. Under the high temperatures employed during epitaxial growth, a significant change in pore morphology occurs. While no evidence of reduced screw dislocation density in the epilayers is obtained, a small tilt of the epilayers with respect to the porous substrate observed on x-ray topographs could play a role in limiting penetration of defects from the substrate.

Strained Layer Epitaxy on Rough Si Surfaces

1995 ◽  
Vol 379 ◽  
Author(s):  
T.D. Lowes ◽  
M. Zinke-Allmang
Keyword(s):  
Epitaxial Layer ◽  
Critical Thickness ◽  
Lattice Mismatch ◽  
Rough Surfaces ◽  
Misfit Strain ◽  
Surface Roughening ◽  
Epitaxial Layers ◽  
Dislocation Generation ◽  
Surface Features ◽  
Initial Substrate

ABSTRACTLattice mismatch associated with heteroepitaxy imposes a significant limitation on the epitaxial compatibility between overlayer and substrate. In lattice mismatched systems the misfit may be accommodated to some extent by strain. However, in order to maintain misfit strain and avoid dislocation generation the epitaxial layer must not exceed a critical thickness. Some success has been reported in avoiding damaged epitaxial layers with thicknesses greater than the critical thickness by overgrowing on patterned or rough surfaces. For the case of Si, surface roughening by energetic Ar+ bombardment as a pre-growth roughening treatment is discussed and assessed. Evolution of surface features as a function of initial substrate treatment, ion accelerating potential, and the duration of bombardment are presented. Stability of the surface features generated by bombardment for typical overgrowth conditions was tested to assess feasibility of this technique for Si heteroepitaxy.

Optimisation of Epitaxial Layer Growth with HCl Addition by Optical and Electrical Characterization

2007 ◽  
Vol 556-557 ◽  
pp. 137-140 ◽  
Author(s):  
Lucia Calcagno ◽  
Gaetano Izzo ◽  
Grazia Litrico ◽  
G. Galvagno ◽  
A. Firrincieli ◽  
...  
Keyword(s):  
Epitaxial Layer ◽  
Growth Process ◽  
Electrical Characterization ◽  
High Growth ◽  
High Growth Rate ◽  
Layer Growth ◽  
Epitaxial Layers ◽  
Electrical Measurements ◽  
Deposition Chamber ◽  
Order Of Magnitude

High growth rate of 4H-SiC epitaxial layers can be reached with the introduction of HCl in the deposition chamber. The effect of the Cl/Si ratio on this epitaxial growth process has been studied by optical and electrical measurements. Optical microscopy shows an improvement of the surface morphology and luminescence measurements reveal a decrease of epitaxial layer defects with increasing the Cl/Si ratio in the range 0.05–2.0. The leakage current measured on the diodes realized on these wafers is reduced of an order of magnitude and DLTS measurements show a decrease of the EH6,7 level concentration in the same range of Cl/Si ratio. The value Cl/Si=2.0 allows to grow epitaxial layers with the lowest defect concentration.

Characterization of Gasb-Based Alloy Semiconductors

1990 ◽  
Vol 216 ◽  
Author(s):  
H. Uekita ◽  
N. Kitamura ◽  
M. Ichimura ◽  
A. Usami ◽  
T. Wada
Keyword(s):  
Raman Spectroscopy ◽  
Liquid Phase ◽  
Epitaxial Layer ◽  
Structural Defects ◽  
Epitaxial Layers ◽  
X Ray Diffraction ◽  
Double Crystal ◽  
X Ray ◽  
Alloy Semiconductors

ABSTRACTGaSb, AlxGa1-xSb, and AlxGa1-xSb epitaxial layers were grown by the liquid-phase epitaxy and characterized by photoluminescence, Raman spectroscopy, and double-crystal X-ray diffraction. The concentration of residual acceptors which are related to structural defects decreased with lowering growth temperature, but the GaSb epitaxial layer grown at an extremely low temperature of 270°C had poor crystalline quality. The AlxGa1-xSb (x≥0.15) and AlxGa1-xSb (x=0.02) epitaxial layers grown at 270 °C, however, had much better quality than the GaSb epitaxial layer grown at the same temperature.

PERFORMANCE OF PSEUDOMORPHIC ULTRAVIOLET LEDs GROWN ON BULK ALUMINUM NITRIDE SUBSTRATES

2011 ◽  
Vol 20 (03) ◽  
pp. 497-504 ◽  
Author(s):  
SHAWN R. GIBB ◽  
JAMES R. GRANDUSKY ◽  
MARK MENDRICK ◽  
LEO J. SCHOWALTER
Keyword(s):  
Dislocation Density ◽  
Published Data ◽  
Epitaxial Layers ◽  
Device Structure ◽  
Low Dislocation Density ◽  
High Aluminum Content ◽  
Current Densities ◽  
Pseudomorphic Growth ◽  
High Aluminum

Low dislocation density pseudomorphic epitaxial layers of Al x Ga 1- x N have been grown on c -face AlN substrates prepared from high quality bulk crystals. As reported previously, pseudomorphic growth yields very low dislocation density layers with atomically smooth surfaces throughout the active region of a full LED device structure. An advantage of the low dislocation density is the ability to n -type dope the high aluminum content Al x Ga 1- x N (x ~ 70%) epitaxial layers required for UVLED devices to obtain sheet resistances less than 350 Ohm/square for 0.5 μm thick layers. Here, we report on the characterization of our pseudomorphic epitaxial AlGaN layers via cathodoluminescence (CL) and on-wafer and initial packaged level characterization of fully fabricated pseudomorphic ultraviolet LEDs (PUVLEDs) with an emission wavelength between 250 - 265 nm. An additional benefit of PUVLED devices is the ability to run these devices at high input powers and current densities. Further, the aforementioned low dislocation density of the epitaxial structure results in improved device performance over previously published data. Mean output powers of greater than 4 mW were obtained on-wafer prior to thinning and roughening while output powers as high as 45 mW were achieved for packaged devices.

Electrical characterization of Schottky diodes fabricated on SiC epitaxial layers grown on porous SiC substrates

2001 ◽  
Vol 184 (1-4) ◽  
pp. 483-486 ◽  
Author(s):  
N.I Kuznetsov ◽  
M.G Mynbaeva ◽  
G Melnychuk ◽  
V.A Dmitriev ◽  
S.E Saddow
Keyword(s):  
Schottky Diodes ◽  
Electrical Characterization ◽  
Epitaxial Layers ◽  
Porous Sic

The Use of Advanced Analytical Techniques for Characterization of the Chemical, Physical, and Crystallographic Nature of a Surface

1973 ◽  
Vol 31 ◽  
pp. 132-133 ◽  
Author(s):  
R. E. Herfert
Keyword(s):  
Surface Characterization ◽  
Analytical Techniques ◽  
X Ray Diffraction ◽  
Depth Of Penetration ◽  
X Ray ◽  
The Past ◽  
Transmission Electron ◽  
Scanning Electron

Studies of the nature of a surface, either metallic or nonmetallic, in the past, have been limited to the instrumentation available for these measurements. In the past, optical microscopy, replica transmission electron microscopy, electron or X-ray diffraction and optical or X-ray spectroscopy have provided the means of surface characterization. Actually, some of these techniques are not purely surface; the depth of penetration may be a few thousands of an inch. Within the last five years, instrumentation has been made available which now makes it practical for use to study the outer few 100A of layers and characterize it completely from a chemical, physical, and crystallographic standpoint. The scanning electron microscope (SEM) provides a means of viewing the surface of a material in situ to magnifications as high as 250,000X.

Some applications of electron beam microanalysis techniques in VLSI process evaluation

1983 ◽  
Vol 41 ◽  
pp. 160-161
Author(s):  
Simon Thomas
Keyword(s):  
Integrated Circuits ◽  
Process Evaluation ◽  
Large Scale ◽  
Technology Development ◽  
Analytical Techniques ◽  
Successful Implementation ◽  
Analysis Of Failures ◽  
Characterization Of Materials ◽  
Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

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