Independent Tunneling Reductions Relative to Homogeneous Oxide Dielectrics From i) Nitrided Interfaces, and ii) Physically-Thicker Stacked Oxide/Nitride and Oxide/Oxynitride Gate Dielectrics

1999 ◽  
Vol 592 ◽  
Author(s):  
Gerry Lucovsky ◽  
Yider Wu ◽  
Yi-Mu Lee ◽  
Hanyang Yang ◽  
Hiro Niimi
Keyword(s):  
Silicon Nitride ◽  
Gate Dielectrics ◽  
Plasma Processing ◽  
Tunneling Current ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Remote Plasma ◽  
Thermally Grown Oxides ◽  
Interfacial Layers ◽  
Direct Tunneling

ABSTRACTDirect tunneling limits aggressive scaling of thermally-grown oxides to about 1.6 nm, a thickness at which the tunneling current. Jg, at one volt is ∼1 A/cm2. This paper presents results that demonstrate that stacked gate dielectrics prepared by remote plasma processing that include i) ultra-thin nitrided SiO2 interfacial layers, and ii) either silicon nitride or oxynitride bulk dielectrics can extend the equivalent oxide thickness, EOT, to 1.1-1.0 nm before Jg, > 1 A/cm2.

Current conduction of 0.72 nm equivalent-oxide-thickness LaO/HfO2 stacked gate dielectrics

2009 ◽  
Vol 95 (1) ◽  
pp. 012103 ◽  
Author(s):  
Chuan-Hsi Liu ◽  
Hung-Wen Chen ◽  
Shung-Yuan Chen ◽  
Heng-Sheng Huang ◽  
Li-Wei Cheng
Keyword(s):  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Current Conduction

The Effect of Ternary Material (Zr, Y, and O) High-k Gate Dielectrics

2013 ◽  
Vol 699 ◽  
pp. 422-425 ◽  
Author(s):  
K.C. Lin ◽  
C.H. Chou ◽  
J.Y. Chen ◽  
C.J. Li ◽  
J.Y. Huang ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Electrical Property ◽  
Leakage Current ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Gate Dielectrics ◽  
Bottom Layer ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
High K

In this research, the Y2O3 layer is doped with the zirconium through co-sputtering and rapid thermal annealing (RTA) at 550°C, 700°C, and 850°C. Then the Al electrode is deposited to generate two kinds of structures, Al/ZrN/ Y2O3/ Y2O3+Zr/p-Si and Al/ZrN/ Y2O3+Zr/ Y2O3/p-Si. According to the XRD results, when Zr was doped on the upper layer, the crystallization phenomenon was more significant than Zr was at the bottom layer, meaning that Zr may influence the diffusion of the oxygen. The AFM also shows that the surface roughness of Zr has worse performance. For the electrical property, the influence to overall leakage current is increased because the equivalent oxide thickness (EOT) is thinner.

Advantage of further scaling in gate dielectrics below 0.5nm of equivalent oxide thickness with La2O3 gate dielectrics

2010 ◽  
Vol 50 (6) ◽  
pp. 790-793 ◽  
Author(s):  
K. Kakushima ◽  
K. Tachi ◽  
P. Ahmet ◽  
K. Tsutsui ◽  
N. Sugii ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness

High Permittivity Oxide Gate Stacks on Silicon Incorporating UHV Silicon Nitride Interfacial Layers

2001 ◽  
Vol 670 ◽  
Author(s):  
Mark A. Shriver ◽  
Ann M. Gabrys ◽  
T. K. Higman ◽  
S. A. Campbell
Keyword(s):  
Oxide Thickness ◽  
Interface State ◽  
Nitride Layer ◽  
State Density ◽  
Interface State Density ◽  
Equivalent Oxide Thickness ◽  
Gate Stacks ◽  
High Permittivity ◽  
Interfacial Layers ◽  
Thermal Nitridation

ABSTRACTCurrent high permittivity material deposition techniques produce a low permittivity oxide interfacial layer consequently increasing the equivalent oxide thickness. This interfacial oxide layer can be prevented by initially growing a thin nitride layer to act as a diffusion barrier. The interfacial nitride layer must also have low interface state densities comparable to state-of-the-art SiO2 insulators in order to be suitable for MOSFETs. The nitride layer used in this study was formed by thermal nitridation in a UHV system, with the subsequent high permittivity deposition done in an adjoining system. After forming capacitors from these films, capacitance vs. voltage (C-V) techniques were used to determine the interface state density and equivalent oxide thickness of the films. Gate stack films were produced on Si(100) and Si(111) and the results are compared. Gate stacks on Si(100) show a slight increase in stretchout in the high frequency C-V curves for both n-type and p-type samples. Initial data suggests that Si(111) has a lower interface state density than the Si(100) gate stacks. This may be attributed to the Si3N4layer on Si(111) being epitaxial nitride.

Preparation of High-Quality Ultra-Thin Gate Dielectrics by Cat-CVD and Catalytic Anneal

1999 ◽  
Vol 606 ◽  
Author(s):  
Hidekazu Satot ◽  
Akira Izumit ◽  
Hideki Matsumura
Keyword(s):  
Hysteresis Loop ◽  
Catalytic Cracking ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Breakdown Field ◽  
Equivalent Oxide Thickness ◽  
Insulating Films ◽  
Mis Diode ◽  
Post Deposition

AbstractThis paper reports a feasibility of Cat-CVD system for improvement in characteristics of ultra thin gate dielectrics. Particularly, the effects of post deposition catalytic anneal (Catanneal) by using hydrogen (H2)-decomposed species or NH3-decomposed species produced by catalytic cracking of H2 or NH3, are investigated. The C-V characteristics are measured by MIS diode for the 4.5nm-thick Cat-CVD SiNx and 8nm-thick sputtered SiO2 for comparison. The small hysteresis loop is seen in the C-V curve of both SiNx and SiO2 films as deposition. However, it is improved by the Cat-anneal using H2 or NH3, and the hysteresis loop completely disappears from the C-V curves for both films. This result demonstrates that the Cat-anneal is a powerful technique to improve quality of insulating films, such as Cat-CVD SiNx and even sputtered SiO2 films. In addition, the leakage current of SiNx, films with 2.8nm equivalent oxide thickness is decreased by several orders of magnitude than that of the conventional thermal SiO2 of similar EOT and the breakdown field is increased several MV/cm by Cat-anneal at 300°C.

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