Preparation of High-Quality Ultra-Thin Gate Dielectrics by Cat-CVD and Catalytic Anneal

1999 ◽  
Vol 606 ◽  
Author(s):  
Hidekazu Satot ◽  
Akira Izumit ◽  
Hideki Matsumura
Keyword(s):  
Hysteresis Loop ◽  
Catalytic Cracking ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Breakdown Field ◽  
Equivalent Oxide Thickness ◽  
Insulating Films ◽  
Mis Diode ◽  
Post Deposition

AbstractThis paper reports a feasibility of Cat-CVD system for improvement in characteristics of ultra thin gate dielectrics. Particularly, the effects of post deposition catalytic anneal (Catanneal) by using hydrogen (H2)-decomposed species or NH3-decomposed species produced by catalytic cracking of H2 or NH3, are investigated. The C-V characteristics are measured by MIS diode for the 4.5nm-thick Cat-CVD SiNx and 8nm-thick sputtered SiO2 for comparison. The small hysteresis loop is seen in the C-V curve of both SiNx and SiO2 films as deposition. However, it is improved by the Cat-anneal using H2 or NH3, and the hysteresis loop completely disappears from the C-V curves for both films. This result demonstrates that the Cat-anneal is a powerful technique to improve quality of insulating films, such as Cat-CVD SiNx and even sputtered SiO2 films. In addition, the leakage current of SiNx, films with 2.8nm equivalent oxide thickness is decreased by several orders of magnitude than that of the conventional thermal SiO2 of similar EOT and the breakdown field is increased several MV/cm by Cat-anneal at 300°C.

Current conduction of 0.72 nm equivalent-oxide-thickness LaO/HfO2 stacked gate dielectrics

2009 ◽  
Vol 95 (1) ◽  
pp. 012103 ◽  
Author(s):  
Chuan-Hsi Liu ◽  
Hung-Wen Chen ◽  
Shung-Yuan Chen ◽  
Heng-Sheng Huang ◽  
Li-Wei Cheng
Keyword(s):  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Current Conduction

The Effect of Ternary Material (Zr, Y, and O) High-k Gate Dielectrics

2013 ◽  
Vol 699 ◽  
pp. 422-425 ◽  
Author(s):  
K.C. Lin ◽  
C.H. Chou ◽  
J.Y. Chen ◽  
C.J. Li ◽  
J.Y. Huang ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Electrical Property ◽  
Leakage Current ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Gate Dielectrics ◽  
Bottom Layer ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
High K

In this research, the Y2O3 layer is doped with the zirconium through co-sputtering and rapid thermal annealing (RTA) at 550°C, 700°C, and 850°C. Then the Al electrode is deposited to generate two kinds of structures, Al/ZrN/ Y2O3/ Y2O3+Zr/p-Si and Al/ZrN/ Y2O3+Zr/ Y2O3/p-Si. According to the XRD results, when Zr was doped on the upper layer, the crystallization phenomenon was more significant than Zr was at the bottom layer, meaning that Zr may influence the diffusion of the oxygen. The AFM also shows that the surface roughness of Zr has worse performance. For the electrical property, the influence to overall leakage current is increased because the equivalent oxide thickness (EOT) is thinner.

Electrical Characteristics of Crystalline Gd2O3 Film on Si (111): Impacts of Growth Temperature and Post Deposition Annealing

2010 ◽  
Vol 1252 ◽  
Author(s):  
Gang Niu ◽  
Bertrand Vilquin ◽  
Nicolas Baboux ◽  
Guillaume Saint-Girons ◽  
Carole Plossu ◽  
...  
Keyword(s):  
Molecular Beam ◽  
Defect Density ◽  
Oxide Thickness ◽  
Electrical Characteristics ◽  
Equivalent Oxide Thickness ◽  
Optimal Temperature ◽  
Post Deposition Annealing ◽  
High K ◽  
Electrical Characterizations ◽  
Post Deposition

AbstractThis work reports on the epitaxial growth of crystalline high-k Gd2O3 on Si (111) by Molecular Beam Epitaxy (MBE) for CMOS gate application. Epitaxial Gd2O3 films of different thicknesses have been deposited on Si (111) between 650°C~750°C. Electrical characterizations reveal that the sample grown at the optimal temperature (700°C) presents an equivalent oxide thickness (EOT) of 0.73nm with a leakage current density of 3.6×10-2 A/cm2 at |Vg-VFB|=1V. Different Post deposition Annealing (PDA) treatments have been performed for the samples grown under optimal condition. The Gd2O3 films exhibit good stability and the PDA process can effectively reduce the defect density in the oxide layer, which results in higher performances of the Gd2O3/Si (111) capacitor.

Advantage of further scaling in gate dielectrics below 0.5nm of equivalent oxide thickness with La2O3 gate dielectrics

2010 ◽  
Vol 50 (6) ◽  
pp. 790-793 ◽  
Author(s):  
K. Kakushima ◽  
K. Tachi ◽  
P. Ahmet ◽  
K. Tsutsui ◽  
N. Sugii ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness

Independent Tunneling Reductions Relative to Homogeneous Oxide Dielectrics From i) Nitrided Interfaces, and ii) Physically-Thicker Stacked Oxide/Nitride and Oxide/Oxynitride Gate Dielectrics

1999 ◽  
Vol 592 ◽  
Author(s):  
Gerry Lucovsky ◽  
Yider Wu ◽  
Yi-Mu Lee ◽  
Hanyang Yang ◽  
Hiro Niimi
Keyword(s):  
Silicon Nitride ◽  
Gate Dielectrics ◽  
Plasma Processing ◽  
Tunneling Current ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Remote Plasma ◽  
Thermally Grown Oxides ◽  
Interfacial Layers ◽  
Direct Tunneling

ABSTRACTDirect tunneling limits aggressive scaling of thermally-grown oxides to about 1.6 nm, a thickness at which the tunneling current. Jg, at one volt is ∼1 A/cm2. This paper presents results that demonstrate that stacked gate dielectrics prepared by remote plasma processing that include i) ultra-thin nitrided SiO2 interfacial layers, and ii) either silicon nitride or oxynitride bulk dielectrics can extend the equivalent oxide thickness, EOT, to 1.1-1.0 nm before Jg, > 1 A/cm2.

Rare Earth Oxide Capping Effect on La$_{2}$O$_{3}$ Gate Dielectrics for Equivalent Oxide Thickness Scaling toward 0.5 nm

2011 ◽  
Vol 50 (10) ◽  
pp. 10PA04 ◽  
Author(s):  
Miyuki Kouda ◽  
Kuniyuki Kakushima ◽  
Parhat Ahmet ◽  
Kazuo Tsutsui ◽  
Akira Nishiyama ◽  
...  
Keyword(s):  
Rare Earth ◽  
Gate Dielectrics ◽  
Rare Earth Oxide ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness
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