ELectrical Characterization of Beryllium Doped Low Temperature MBE Grown GaAs

1999 ◽  
Vol 570 ◽  
Author(s):  
M. J. Cich ◽  
R. Zhao ◽  
Y. Park ◽  
P. Specht ◽  
E. R. Weber
Keyword(s):  
Electrical Properties ◽  
Low Temperature ◽  
Barrier Height ◽  
Growth Temperature ◽  
Electrical Characterization ◽  
Breakdown Field ◽  
Current Rise ◽  
Beryllium Doping ◽  
Lt Gaas

ABSTRACTThe electrical properties of low temperature MBE grown GaAs (LT-GaAs) in the n-i-n configuration have been studied. The mechanism of current rise in beryllium doped LT-GaAs is found to fit Frenkel-Poole type emission with a barrier height of 0.26 eV. However, this model does not fit undoped LT-GaAs. The breakdown field is considerably higher (up to 5.2* 105 V/cm) for beryllium doped films than undoped films, and depends on both growth temperature and beryllium concentration. Beryllium doping is also found to increase the resistivity of the preannealed films to values > 109 ω-cm.

Electrical Characterization of Low Temperature GaAs Layers, and Observation of the Extremely Large Carrier Concentrations in Undoped Material

1991 ◽  
Vol 241 ◽  
Author(s):  
Bijan Tadayon ◽  
Mohammad Fatemi ◽  
Saied Tadayon ◽  
F. Moore ◽  
Harry Dietrich
Keyword(s):  
Molecular Beam Epitaxy ◽  
Low Temperature ◽  
Substrate Temperature ◽  
Molecular Beam ◽  
Electrical Characterization ◽  
Physical Characteristics ◽  
Hall Measurements ◽  
Undoped Material ◽  
Low Temperature Gaas

ABSTRACTWe present here the results of a study on the effect of substrate temperature, Ts, on the electrical and physical characteristics of low temperature (LT) molecular beam epitaxy GaAs layers. Hall measurements have been performed on the asgrown samples and on samples annealed at 610 °C and 850 °C. Si implantation into these layers has also been investigated.

Characterization of Thermal Oxides of Laser Annealed Polysilicon

1981 ◽  
Vol 4 ◽  
Author(s):  
Rajiv R. Shah ◽  
Robert Mays ◽  
D. Lloyd Crosthwait
Keyword(s):  
Laser Processing ◽  
Single Crystal Silicon ◽  
Electrical Characterization ◽  
Device Fabrication ◽  
Breakdown Field ◽  
Guard Ring ◽  
Crystal Silicon ◽  
Process Sequence ◽  
Thermal Oxide

ABSTRACTWe report an investigation of the effects of laser processing on the thermal oxides of polysilicon. LPCVD polysilicon, 500 nm thick, deposited on 500 nm thermal oxide of single crystal silicon was laser processed at various stages in the process sequence for device fabrication. Effects of CW Ar+ and pulsed 1.06 and 0.53 μm laser processing were investigated. Laser annealed polysilicon was oxidized in a steam ambient. Using a second level of polysilicon, guard ring diode and capacitors were fabricated. Electrical characterization revealed an improvement in breakdown field strengths of these oxides without deleterious effects on any of the associated interfaces.

Electrical Characterization of the Graphene-SiC Heterojunction

2012 ◽  
Vol 717-720 ◽  
pp. 641-644
Author(s):  
Travis J. Anderson ◽  
Karl D. Hobart ◽  
Luke O. Nyakiti ◽  
Virginia D. Wheeler ◽  
Rachael L. Myers-Ward ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Charge Carrier ◽  
Graphene Sheet ◽  
Carrier Transport ◽  
Electrical Characterization ◽  
Epitaxial Graphene ◽  
Charge Carrier Transport ◽  
Semiconductor System ◽  
Significant Research

Graphene, a 2D material, has motivated significant research in the study of its in-plane charge carrier transport in order to understand and exploit its unique physical and electrical properties. The vertical graphene-semiconductor system, however, also presents opportunities for unique devices, yet there have been few attempts to understand the properties of carrier transport through the graphene sheet into an underlying substrate. In this work, we investigate the epitaxial graphene/4H-SiC system, studying both p and n-type SiC substrates with varying doping levels in order to better understand this vertical heterojunction.

Investigation of carrier transport mechanisms in the Cu–Zn–Se based hetero-structure grown by sputtering technique

2018 ◽  
Vol 96 (7) ◽  
pp. 816-825 ◽  
Author(s):  
H.H. Güllü ◽  
M. Terlemezoğlu ◽  
Ö. Bayraklı ◽  
D.E. Yıldız ◽  
M. Parlak
Keyword(s):  
Barrier Height ◽  
Carrier Transport ◽  
Thermionic Emission ◽  
Electrical Characterization ◽  
Band Gap Energy ◽  
Zero Bias ◽  
Hetero Structure ◽  
Current Voltage ◽  
P Type

In this paper, we present results of the electrical characterization of n-Si/p-Cu–Zn–Se hetero-structure. Sputtered film was found in Se-rich behavior with tetragonal polycrystalline nature along with (112) preferred orientation. The band gap energy for direct optical transitions was obtained as 2.65 eV. The results of the conductivity measurements indicated p-type behavior and carrier transport mechanism was modelled according to thermionic emission theory. Detailed electrical characterization of this structure was carried out with the help of temperature-dependent current–voltage measurements in the temperature range of 220–360 K, room temperature, and frequency-dependent capacitance–voltage and conductance-voltage measurements. The anomaly in current–voltage characteristics was related to barrier height inhomogeneity at the interface and modified by the assumption of Gaussian distribution of barrier height, in which mean barrier height and standard deviation at zero bias were found as 2.11 and 0.24 eV, respectively. Moreover, Richardson constant value was determined as 141.95 Acm−2K−2 by means of modified Richardson plot.

Electrical Characterization of Low Temperature PECVD Oxides for TSV Applications

2018 ◽  
Vol 2018 (1) ◽  
pp. 000728-000733
Author(s):  
Piotr Mackowiak ◽  
Rachid Abdallah ◽  
Martin Wilke ◽  
Jash Patel ◽  
Huma Ashraf ◽  
...  
Keyword(s):  
Low Temperature ◽  
Electrical Characterization ◽  
Chemical Vapor ◽  
Silicon Substrates ◽  
Low Temperature Plasma ◽  
Temperature Plasma ◽  
Charge Densities ◽  
Doped Silicon

Abstract In the present work we investigate the quality of low temperature Plasma Enhanced Chemical Vapor Deposition (PECVD) and plasma treated Tetraethyl orthosilicate (TEOS)-based TSV-liner films. Different designs of Trough Silicon Via (TSV) Test structures with 10μm and 20μm width and a depth of 100μm have been fabricated. Two differently doped silicon substrates have been used – highly p-doped and moderately doped. The results for break-through, resistivity and capacitance for the 20μm structures show a better performance compared to the 10μm structures. This is mainly due to increased liner thickness in the reduced aspect ratio case. Lower interface traps and oxide charge densities have been observed in the C-V measurements results for the 10μm structures.

Electrical Characterization of In Schottky Contacts to Epitaxial n-In0.46Ga0.54P Grown on n+-GaAs by Mocvd

1996 ◽  
Vol 448 ◽  
Author(s):  
N. Marcano ◽  
A. Singh
Keyword(s):  
Barrier Height ◽  
Thermionic Emission ◽  
Electrical Characterization ◽  
Interface Layer ◽  
Zero Bias ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Direct Current Voltage ◽  
Etched Surface

AbstractIn/n-In0.46Ga0.54P Schottky diode was fabricated by thermal evaporation of In on chemically etched surface of In0.45Ga0.54P:Si epitaxial layer grown on highly doped n type GaAs. The In metal formed a high quality rectifying contact to In0.46Ga0.54P:Si with a rectification ratio of 500. The direct current-voltage/temperature (I-V/T) characteristics were non-ideal with the values of the ideality factor (n) between 1.26-1.78 for 400>T>260 K. The forward I-V data strongly indicated that the current was controlled by the generation-recombination (GR) and thermionic emission (TE) mechanisms for temperature in the range 260-400 K. From the temperature variation of the TE reverse saturation current, the values of (0.75±0.05)V and the (4.5±0.5)×10-5 Acm-2K-2 for the zero bias zero temperature barrier height (φoo) and modified effective Richardson constant were obtained. The 1 MHz capacitance-voltage (C-V) data for 260 K < T < 400 K was analyzed in terms of the C-2-V relation including the effect of interface layer to obtain more realistic values of the barrier height (φbo). The temperature dependence of φbo was described the relation φbo =(0.86±10.03) - (8.4±0.7)×l0-4T. The values of φoo, obtained by the I-V and C-V techniques agreed well.

Electrical characterization of low‐temperature Al0.3Ga0.7As using n‐i‐n structures

1996 ◽  
Vol 68 (5) ◽  
pp. 699-701 ◽  
Author(s):  
A. K. Verma ◽  
J. Tu ◽  
J. S. Smith ◽  
H. Fujioka ◽  
E. R. Weber
Keyword(s):  
Low Temperature ◽  
Electrical Characterization

Low-Temperature Processing Using Triple Alkoxide Precursors for Layer-Structured Perovskite Thin Films: Preparation and Characterization of Mbi2Ta2O9 (M: Ca or Ba) Thin Films

1999 ◽  
Vol 596 ◽  
Author(s):  
K. Kato
Keyword(s):  
Crystal Structure ◽  
Thin Films ◽  
Electrical Properties ◽  
Low Temperature ◽  
Surface Topography ◽  
Annealing Temperature ◽  
Low Temperature Processing ◽  
Deposited Films ◽  
Alkoxide Precursors

AbstractCaBi2Ta2O9 and BaBi2Ta2O9 thin films were successfully prepared by using triple alkoxide precursors such as Ca[BiTa(OC2H5)9]2 and Ba[BiTa(OC2H5)9]2, respectively. As-deposited films were amorphous and crystallized below 500°C by rapid thermal annealing in oxygen. The crystallinity improved with annealing temperature. The development of the crystal structure and surface topography of the thin films were investigated. Additionally, some electrical properties were evaluated.

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