Breakdown Characteristics of Ultra-Thin Gate Oxides Caused by Plasma Charging

1999 ◽  
Vol 567 ◽  
Author(s):  
Chi-Chun Chen ◽  
Horng-Chih Lin ◽  
Chun-Yen Chang ◽  
Chao-Hsin Chien ◽  
Tiao-Yuan Huang

ABSTRACTBreakdown characteristics of ultra-thin gate oxides caused by plasma charging were studied in this work. It is observed that as oxide thickness is scaled down to 4 nm, some traditional monitor parameters may lose their sensitivity for detecting oxide degradation induced by plasma charging damage, due to insignificant trap generation. Even the gate leakage current, although sensitive for 4 nm oxide, may no longer be sensitive enough for even thinner oxide (e.g., 2.6 nm), due to the existence of large tunneling current. Moreover, several soft-breakdown events were found to occur in ultrathin oxide before the final onset of a catastrophic hard-breakdown. Finally, an equivalent local oxide thickness is calculated using local oxide thinning model to estimate the stepwise increase of gate current after soft-breakdown event.

2006 ◽  
Vol 917 ◽  
Author(s):  
Zhi Chen ◽  
Jun Guo ◽  
Chandan B Samantaray

AbstractWe study in detail a newly discovered effect, phonon-energy-coupling enhancement (PECE) effect, produced by rapid thermal processing (RTP). It includes two aspects: (1) Strengthening Si-D bonds and Si-O bonds and (2) Change of energy band structure and effective mass due to thermal shock. It is shown that not only Si-D bonds but also Si-O bonds have been strengthened dramatically, leading to enhancement of robustness of the oxide structure and the oxide/Si interface. For thick oxides (>3 nm), the gate leakage current has been reduced by two orders of magnitude and the breakdown voltage has been improved by ~30% due to phonon-energy coupling. For ultrathin oxides (2.2 nm), the direct tunneling current has been reduced by five-orders of magnitude, equivalent to that of HfO2, probably due to the increased effective mass and barrier height.


2011 ◽  
Vol 20 (08) ◽  
pp. 1659-1675 ◽  
Author(s):  
ASHWANI K. RANA ◽  
NAROTTAM CHAND ◽  
VINOD KAPOOR

Dimensions of metal–oxide–semiconductor field effect transistor (MOSFET) have been scaled down for decades to maintain the performance. So, as a result of aggressive scaling, gate oxide thickness approaches its manufacturing and physically limiting value of less than 2 nm in nano regime. Under such circumstances, gate leakage (tunneling) current has become a critical problem in nano domain as compared to subthreshold leakage current. Consequently, accurate quantitative understanding of gate tunneling leakage current is very important especially in context of low power VLSI application. In this work, gate tunneling currents have been modeled including the inevitable nano scale effects for a MOSFET having different high-k dielectric spacer such as SiO2 , Si3N4 , Al2O3 , HfO2 . The gate current model is compared and contrasted with santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed that neglecting nano scale effects may lead to large error in the calculated gate current. It is found in the results that gate leakage current decreases with the increase of dielectric constant of the gate spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering, and subthreshold slope of the device.


2000 ◽  
Vol 47 (3) ◽  
pp. 566-573 ◽  
Author(s):  
M. Ceschia ◽  
A. Paccagnella ◽  
S. Sandrin ◽  
G. Ghidini ◽  
J. Wyss ◽  
...  

2011 ◽  
Vol 88 (7) ◽  
pp. 1309-1311 ◽  
Author(s):  
C.H. Fu ◽  
K.S. Chang-Liao ◽  
Y.A. Chang ◽  
Y.Y. Hsu ◽  
T.H. Tzeng ◽  
...  

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