Integration Challenges of Inorganic Low-K (K≤2.5) Materials with Cu for Sub-0.25µm Multilevel Interconnects

1999 ◽  
Vol 564 ◽  
Author(s):  
K. C. Yu ◽  
J. Defilippi ◽  
R. Tiwari ◽  
T. Sparks ◽  
D. Smith ◽  
...  

AbstractThe recent introduction of dual inlaid Cu and oxide based interconnects within sub-0.25μm CMOS technology has delivered higher performance and lower power devices. Further speed improvements and power reduction may be achieved by reducing the interconnect parasitic capacitance through integration of low-k interlevel dielectric (ILD) materials with Cu. This paper demonstrates successful multi-level dual inlaid Cu/low-k interconnects with ILD permittivities ranging from 2.0 to 2.5. Integration challenges specific to inorganic low-k and Cu based structures are discussed. Through advanced CMP process development, multi-level integration of porous oxide materials with moduli less than 0.5 GPa is demonstrated. Parametric data and isothermal annealing of these Cu/ low-k structures show results with yield comparable to Cu/oxide based interconnects.

1999 ◽  
Vol 565 ◽  
Author(s):  
K. C. Yu ◽  
J. Defilippi ◽  
R. Tiwari ◽  
T. Sparks ◽  
D. Smith ◽  
...  

AbstractThe recent introduction of dual inlaid Cu and oxide based interconnects within sub-0.25μm CMOS technology has delivered higher performance and lower power devices. Further speed improvements and power reduction may be achieved by reducing the interconnect parasitic capacitance through integration of low-k interlevel dielectric (ILD) materials with Cu. This paper demonstrates successful multi-level dual inlaid Cu/low-k interconnects with ILD permittivities ranging from 2.0 to 2.5. Integration challenges specific to inorganic low-k and Cu based structures are discussed. Through advanced CMP process development, multi-level integration of porous oxide materials with moduli less than 0.5 GPa is demonstrated. Parametric data and isothermal annealing of these Cu/ low-k structures show results with yield comparable to Cu/oxide based interconnects.


2004 ◽  
Vol 812 ◽  
Author(s):  
Charlie Jun Zhai ◽  
Paul R. Besser ◽  
Frank Feustel

AbstractThe damascene fabrication method and the introduction of low-K dielectrics present a host of reliability challenges to Cu interconnects and fundamentally change the mechanical stress state of Cu lines. In order to capture the effect of individual process steps on the stress evolution in the BEoL (Back End of Line), a process-oriented finite element modeling (FEM) approach was developed. In this model, the complete stress history at any step of BEoL can be simulated as a dual damascene Cu structure is fabricated. The inputs to the model include the temperature profile during each process step and materials constants. The modeling results are verified in two ways: through wafer-curvature measurement during multiple film deposition processes and with X-Ray diffraction to measure the mechanical stress state of the Cu interconnect lines fabricated using 0.13um CMOS technology. The Cu line stress evolution is simulated during the process of multi-step processing for a dual damascene Cu/low-K structure. It is shown that the in-plane stress of Cu lines is nearly independent of subsequent processes, while the out-of-plane stress increases considerably with the subsequent process steps.


2008 ◽  
Vol 1 ◽  
pp. 189-196 ◽  
Author(s):  
Sonanvane Avinash ◽  
Bhavana N. Joshi ◽  
Ashok Madhu Mahajan
Keyword(s):  

2001 ◽  
Vol 45 (1) ◽  
pp. 199-203 ◽  
Author(s):  
Chung-Hui Chen ◽  
Yean-Kuen Fang ◽  
Chun-Sheng Lin ◽  
Chih-Wei Yang ◽  
Jang-Cheng Hsieh
Keyword(s):  

Author(s):  
Xiaoli Liu ◽  
Seamus Ober ◽  
Weihua Tang ◽  
Chee-Keong Tan

Wide-gap oxide materials including gallium oxide and aluminium oxide have been attracting much interest due to their tremendous potential for application in power devices. In this work, a new III-oxide...


2017 ◽  
Vol 2017 (1) ◽  
pp. 000491-000496
Author(s):  
Mario Magaña ◽  
Basab Chatterjee ◽  
Rey Javier

Abstract TI's commitment to meeting customer requirements has resulted in the development of package technologies and process to improve performance and higher power at lower cost for wire-bonded packages and automotive products are requiring more stringent reliability requirements. Some of the strategies we have adopted include using thinner metal and low-K ILD for lower parasitics and higher performance, thick copper routings for higher power and larger wafer diameters and smaller scribe streets for lower cost and using Copper (Cu) wire. Cu wire is a key enabler due to higher electrical conductivity and lower cost than gold), but also poses integration challenges due to hardness, CTE mismatch and corrosion susceptibility. The hardness of the copper wire imposes significant challenges for wire-bonding on pads w thin metal and low-k ILD. This required co-design of die bond pad structure for enhanced reliability as well as Cu wire process development requires comprehensive approach encompassing multiple areas including ball and stitch parameters, capillary design, bonding processes like segmented bonding and validation of process margins using ‘hammer’ test. Copper wire also requires metrology and test/detection tools like Nomarski, stitch pull test in addition to the traditional wire pull at mid span and neck, rapid-bake test, measuring intermetallics & Al remaining under ball, and Al-splash. The susceptibility of Cu wire to corrosion required us to introduce new materials like PCC and Au-flash PCC, tight environmental controls in the form of forming gas, monitoring of Ph and ion-trappers in BOM, wire oxidation check at outgoing/incoming inspection as SERA (Sequential Electrochemical Reduction Analysis), and paying close attention to handling and non-process gases. More stringent qualification requirements like AEC-006 is driving additional changes to lead frame design and finish, selection of EMC and Die attach, to reduce delamination and epoxy bleed-out. The demands for lower cost is driving us to use larger sized wafers (like 300mm) and narrower scribe width, while packing more functionality into smaller dies thereby driving higher metal densities. Additional requirements for thinner and 3D packages requiring post backgrind thickness as low as 50–75um imposing challenges in terms of warpage and saw. The demand for higher power applications is requiring us to use thick copper routings. We have developed test structures and redesigned layout of the scribe street and scribe seal and pursuing new saw methods. We have also learned many lessons in terms of handling and corrosion risks and implemented safeguards in terms of process and material selection.


2005 ◽  
Vol 81 (1) ◽  
pp. 75-82 ◽  
Author(s):  
Jonathan Tan ◽  
Zhao Wei Zhong ◽  
Hong Meng Ho

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