scholarly journals Material Requirements for Buffer Layers Used to Obtain Solar Cells with High Open Circuit Voltages

1999 ◽  
Vol 557 ◽  
Author(s):  
Bolko Von Roedern ◽  
Gottfried H. Bauer
Keyword(s):  
Solar Cells ◽  
Transparent Conductive Oxide ◽  
Contact Layer ◽  
Open Circuit ◽  
Buffer Layers ◽  
Hit Cells ◽  
Type C ◽  
P Type ◽  
Open Circuit Voltages ◽  
Material Requirements

AbstractThis paper discusses material requirements for junction layers needed to obtain solar cells with highest possible open-circuit voltages (VOC). In a typical a-Si:H-based “p/i/n” solar cell, this includes the transparent conductive oxide (TCO) contact layer, the p-layer, a “buffer layer” inserted at the p/i interface, and the surface portion of the intrinsic layer. In HIT-cells, the i-layer between (n-type) c-Si and (p-type) a-Si:H may be regarded as the buffer. Our suggestion to obtain high values of VOC relies on using materials with high lifetimes and low carrier mobilities that are capable of reducing surface or junction recombination by reducing the flow of carriers into this loss-pathway. We provide a general calculation that supports these approaches and can explain why these schemes are beneficial for all solar cells.

Solar Cell Contacts Using Nano-Sized Dispersions

1999 ◽  
Vol 581 ◽  
Author(s):  
Doug Schulz ◽  
R. Ribelin ◽  
X. Wu ◽  
K.M. Jones ◽  
R.J. Matson ◽  
...  
Keyword(s):  
Solar Cells ◽  
Spray Deposition ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Cdte Layer ◽  
Open Circuit ◽  
Alloy Formation ◽  
Current Densities ◽  
P Type ◽  
Open Circuit Voltages

ABSTRACTNano-sized dispersions have been employed as precursor inks for the spray deposition of contacts to both Si and CdTe materials. In the case of Si, nano-sized Al particles (nano-Al) were dispersed and spray deposited onto p-type Si. Annealing above the eutectic temperature causes alloy formation yielding a p+ layer with p ∼ 10−4 Ω•cm. For CdTe, nano-sized Te particles (nano-Te) were dispersed and sprayed onto CdTe/CdS/SnO2/glass heterostructures. Contact to the CdTe layer occurred during a 30 min anneal in He (T = 215 to 255 °C). These solar cells were finished by spin-coating the Te layer with Ag paint and subsequently annealing in air (100 °C / 1 h). This approach produces solar cells with open circuit voltages (Voc) from 720 to 800 mV, short circuit current densities (Jsc) from 18 to 20 mA/cm2 and efficiencies up to 10.3%. The performance of these cells was similar to those produced using the standard NREL contact.

Analysis of AgNW-TCO hybrid window electrode for silicon heterojunction solar cells via angular matrix framework

MRS Advances ◽  
2015 ◽  
Vol 1 (59) ◽  
pp. 3897-3902 ◽  
Author(s):  
Zi Ouyang ◽  
Yang Li ◽  
Shouyi Xie ◽  
Alison Lennon
Keyword(s):  
Solar Cells ◽  
Cell Structure ◽  
Transparent Conductive Oxide ◽  
Open Circuit ◽  
Silver Nanowire ◽  
Limiting Factor ◽  
Trade Off ◽  
Heterojunction Solar Cells ◽  
Silicon Based ◽  
Open Circuit Voltages

ABSTRACTSilicon heterojunction (Si-HJT) solar cells are one of the most efficient silicon-based solar cells, due largely to their high open-circuit voltages. For the transparent conductive oxide (TCO) layers, there is a design trade-off between their conductance and their parasitic light absorption, and this trade-off can be a performance-limiting factor for Si-HJT solar cells. It has been demonstrated that silver nanowire (AgNW) networks with superior optical and electrical performances, can complement TCOs. To evaluate the performance of AgNW-TCO hybrid electrodes for Si-HJT cells, it is beneficial to numerically simulate and optimize the optical and electrical performances of the entire device. However, the dimensions of the AgNWs are massively different to the dimensions of the other components of the cells, making individual modeling methods incapable. In this paper, we use an angular matrix framework (AMF) to resolve the challenge, where matrices are used to describe the transition of the angular distribution of the light when it is reflected or transmitted at the interface, or absorbed in the bulk. These matrices pass optical information between nanoscale and microscale components of the cell structure. Using AMF, we calculated the optical properties of the devices, and demonstrated that the AgNW-TCO electrode has advantages over a TCO electrode. Guidance on how the optimization of the composite electrode can be achieved was provided.

scholarly journals Effects of Annealing on Characteristics of Cu2ZnSnSe4/CH3NH3PbI3/ZnS/IZO Nanostructures for Enhanced Photovoltaic Solar Cells

Nanomaterials ◽  
2020 ◽  
Vol 10 (3) ◽  
pp. 521 ◽  
Author(s):  
Chzu-Chiang Tseng ◽  
Gwomei Wu ◽  
Liann-Be Chang ◽  
Ming-Jer Jeng ◽  
Wu-Shiung Feng ◽  
...  
Keyword(s):  
Zinc Oxide ◽  
Solar Cells ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Transparent Conductive Oxide ◽  
Contact Layer ◽  
Open Circuit ◽  
Hole Transporting ◽  
Different Temperatures ◽  
Photovoltaic Solar Cells

This paper presents new photovoltaic solar cells with Cu2ZnSnSe4/CH3NH3PbI3(MAPbI3)/ZnS/IZO/Ag nanostructures on bi-layer Mo/FTO (fluorine-doped tin oxide) glasssubstrates. The hole-transporting layer, active absorber layer, electron-transporting layer, transparent-conductive oxide layer, and top electrode-metal contact layer, were made of Cu2ZnSnSe4, MAPbI3 perovskite, zincsulfide, indium-doped zinc oxide, and silver, respectively. The active absorber MAPbI3 perovskite film was deposited on Cu2ZnSnSe4 hole-transporting layer that has been annealed at different temperatures. TheseCu2ZnSnSe4 filmsexhibitedthe morphology with increased crystal grain sizesand reduced pinholes, following the increased annealing temperature. When the perovskitefilm thickness was designed at 700 nm, the Cu2ZnSnSe4 hole-transporting layer was 160 nm, and the IZO (indium-zinc oxide) at 100 nm, and annealed at 650 °C, the experimental results showed significant improvements in the solar cell characteristics. The open-circuit voltage was increased to 1.1 V, the short-circuit current was improved to 20.8 mA/cm2, and the device fill factor was elevated to 76.3%. In addition, the device power-conversion efficiency has been improved to 17.4%. The output power Pmax was as good as 1.74 mW and the device series-resistance was 17.1 Ω.

scholarly journals Effect of Annealing on the Properties of Antimony Telluride Thin Films and Their Applications in CdTe Solar Cells

2014 ◽  
Vol 2014 ◽  
pp. 1-6
Author(s):  
Zhouling Wang ◽  
Yu Hu ◽  
Wei Li ◽  
Guanggen Zeng ◽  
Lianghuan Feng ◽  
...  
Keyword(s):  
Thin Films ◽  
Solar Cells ◽  
Contact Layer ◽  
Buffer Layers ◽  
Antimony Telluride ◽  
X Ray ◽  
Cdte Solar Cells ◽  
Structural And Electrical Properties ◽  
Different Temperatures ◽  
P Type

Antimony telluride alloy thin films were deposited at room temperature by using the vacuum coevaporation method. The films were annealed at different temperatures in N2ambient, and then the compositional, structural, and electrical properties of antimony telluride thin films were characterized by X-ray fluorescence, X-ray diffraction, differential thermal analysis, and Hall measurements. The results indicate that single phase antimony telluride existed when the annealing temperature was higher than 488 K. All thin films exhibited p-type conductivity with high carrier concentrations. Cell performance was greatly improved when the antimony telluride thin films were used as the back contact layer for CdTe thin film solar cells. The dark current voltage and capacitance voltage measurements were performed to investigate the formation of the back contacts for the cells with or without Sb2Te3buffer layers. CdTe solar cells with the buffer layers can reduce the series resistance and eliminate the reverse junction between CdTe and metal electrodes.

scholarly journals P‐type Upgraded Metallurgical‐Grade Multicrystalline Silicon Heterojunction Solar Cells with Open‐Circuit Voltages over 690 mV

2019 ◽  
Vol 216 (17) ◽  
pp. 1900319 ◽  
Author(s):  
Bruno Vicari Stefani ◽  
William Weigand ◽  
Matthew Wright ◽  
Anastasia Soeriyadi ◽  
Zhengshan (Jason) Yu ◽  
...  
Keyword(s):  
Solar Cells ◽  
Open Circuit ◽  
Multicrystalline Silicon ◽  
Heterojunction Solar Cells ◽  
P Type ◽  
Open Circuit Voltages ◽  
Silicon Heterojunction Solar Cells

Oxygenated CdS Buffer Layers Enabling High Open‐Circuit Voltages in Earth‐Abundant Cu 2 BaSnS 4 Thin‐Film Solar Cells

2016 ◽  
Vol 7 (6) ◽  
pp. 1601803 ◽  
Author(s):  
Jie Ge ◽  
Prakash Koirala ◽  
Corey R. Grice ◽  
Paul J. Roland ◽  
Yue Yu ◽  
...  
Keyword(s):  
Thin Film ◽  
Solar Cells ◽  
Open Circuit ◽  
Buffer Layers ◽  
Thin Film Solar Cells ◽  
Earth Abundant ◽  
Open Circuit Voltages

17.8%-efficient Amorphous Silicon Heterojunction Solar Cells on p-type Silicon Wafers

2006 ◽  
Vol 910 ◽  
Author(s):  
Qi Wang ◽  
Matt P. Page ◽  
Eugene Iwancizko ◽  
Yueqin Xu ◽  
Yanfa Yan ◽  
...  
Keyword(s):  
Solar Cells ◽  
Solar Cell ◽  
Amorphous Silicon ◽  
High Efficiency ◽  
Short Circuit ◽  
Open Circuit ◽  
Layer Growth ◽  
Surface Recombination Velocity ◽  
Back Contact ◽  
P Type

AbstractWe have achieved an independently-confirmed 17.8% conversion efficiency in a 1-cm2, p-type, float-zone silicon (FZ-Si) based heterojunction solar cell. Both the front emitter and back contact are hydrogenated amorphous silicon (a-Si:H) deposited by hot-wire chemical vapor deposition (HWCVD). This is the highest reported efficiency for a HWCVD silicon heterojunction (SHJ) solar cell. Two main improvements lead to our most recent increases in efficiency: 1) the use of textured Si wafers, and 2) the application of a-Si:H heterojunctions on both sides of the cell. Despite the use of textured c-Si to increase the short-circuit current, we were able to maintain the same 0.65 V open-circuit voltage as on flat c-Si. This is achieved by coating a-Si:H conformally on the c-Si surfaces, including covering the tips of the anisotropically-etched pyramids. A brief atomic H treatment before emitter deposition is not necessary on the textured wafers, though it was helpful in the flat wafers. It is essential to high efficiency SHJ solar cells that the emitter grows abruptly as amorphous silicon, instead of as microcrystalline or epitaxial Si. The contact on each side of the cell comprises a thin (< 5 nm) low substrate temperature (~100°C) intrinsic a-Si:H layer, followed by a doped layer. Our intrinsic layers are deposited at 0.3-1.2 nm/s. The doped emitter and back-contact layers were deposited at a higher temperature (>200°C) and grown from PH3/SiH4/H2 and B2H6/SiH4/H2 doping gas mixtures, respectively. This combination of low (intrinsic) and high (doped layer) growth temperatures was optimized by lifetime and surface recombination velocity measurements. Our rapid efficiency advance suggests that HWCVD may have advantages over plasma-enhanced (PE) CVD in fabrication of high-efficiency heterojunction c-Si cells; there is no need for process optimization to avoid plasma damage to the delicate, high-quality, Si wafers.

Liquid-Phase Crystallized Silicon Solar Cells on Glass: Increasing the Open-Circuit Voltage by Optimized Interlayers for n- and p-Type Absorbers

2015 ◽  
Vol 5 (6) ◽  
pp. 1757-1761 ◽  
Author(s):  
Daniel Amkreutz ◽  
William D. Barker ◽  
Sven Kuhnapfel ◽  
Paul Sonntag ◽  
Onno Gabriel ◽  
...  
Keyword(s):  
Solar Cells ◽  
Liquid Phase ◽  
Open Circuit Voltage ◽  
Open Circuit ◽  
Silicon Solar Cells ◽  
P Type
Sign in / Sign up

Export Citation Format

Share Document