The Engineering of Silicon Wafer Material Properties Through Vacancy Concentration Profile Control and the Achievement of Ideal Oxygen Precipitation Behavior

1998 ◽  
Vol 510 ◽  
Author(s):  
R. Falster ◽  
D. Gambaro ◽  
M. Olmo ◽  
M. Cornara ◽  
H. Korb
Keyword(s):  
Silicon Wafer ◽  
Integrated Circuit ◽  
Defect Formation ◽  
Electronic Device ◽  
Vacancy Concentration ◽  
Silicon Wafers ◽  
Precipitation Behavior ◽  
Oxygen Precipitation ◽  
Profile Control ◽  
Zone Depth

AbstractA new kind of silicon wafer and a new class of materials engineering techniques for silicon wafers is described. This wafer, called the “Magic Denuded Zone” or MDZ wafer, is produced through the manipulation of the vacancy concentration and, in particular, vacancy concentration depth profiles in the wafer prior to the development of oxygen precipitates in subsequent heat treatments. The result is a wafer with ideal oxygen precipitation behavior for use in all types of integrated circuit applications. The methods used to prepare such wafers combine Frenkel pair generation with injection and the use of surface sinks. Simulations of the vacancy profiles produced by these techniques are presented and discussed. It is shown that within the range of vacancy concentration accessible by these techniques (up to ca. 1013 cm−3) the rate and oxygen concentration dependence of oxygen clustering can be substantially modified. Such techniques can be used to precisely engineer unique and desirable oxygen-related defect performance in silicon wafers both in terms of distribution and rate of defect formation. One result of the application of such techniques is an ideally precipitating silicon wafer in which the resulting oxygen precipitate profile (denuded zone depth and bulk density of precipitates) is independent of the concentration of oxygen of the wafer, the details of the crystal growth process used to prepare the wafer and, to a very large extent, the details of thermal cycles used to process the wafer into an electronic device. Optimal, generic and reliable internal gettering performance is achieved in such a wafer

Enhanced Internal Gettering of Iron in n/n+ Epitaxial Silicon Wafer: Effect of High Temperature Rapid Thermal Annealing in Nitrogen Ambient

2015 ◽  
Vol 242 ◽  
pp. 218-223
Author(s):  
Peng Dong ◽  
Xing Bo Liang ◽  
Da Xi Tian ◽  
Xiang Yang Ma ◽  
De Ren Yang
Keyword(s):  
Silicon Wafer ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Silicon Wafers ◽  
Enhancement Effect ◽  
Epitaxial Silicon ◽  
High Concentration ◽  
Oxygen Precipitation ◽  
Doped Silicon ◽  
The One

We report a strategy feasible for improving the internal gettering (IG) capability of iron (Fe) for n/n+ epitaxial silicon wafers using the heavily arsenic (As)-doped Czochralski (CZ) silicon wafers as the substrates. The n/n+ epitaxial silicon wafers were subjected to the two-step anneal of 650 °C/16 h + 1000 °C/16 h following the rapid thermal processing (RTP) at 1250 °C in argon (Ar) or nitrogen (N2) atmosphere. It is found that the prior RTP in N2 atmosphere exhibits much stronger enhancement effect on oxygen precipitation (OP) in the substrates than that in Ar atmosphere, thereby leading to a better IG capability of Fe contamination on the epitaxial wafer. In comparison with the RTP in Ar atmosphere, the one in N2 atmosphere injects not only vacancies but also nitrogen atoms of high concentration into the heavily As-doped silicon substrate. The co-action of vacancy and nitrogen leads to the enhanced OP in the substrate and therefore the better IG capability for the n/n+ epitaxial silicon wafer.

Oxygen Precipitation Behavior in 300 mm Polished Czorchralski Silicon Wafers

1999 ◽  
Vol 146 (10) ◽  
pp. 3807-3811 ◽  
Author(s):  
T. Ono ◽  
G. A. Rozgonyi ◽  
C. Au ◽  
T. Messina ◽  
R. K. Goodall ◽  
...  
Keyword(s):  
Silicon Wafers ◽  
Precipitation Behavior ◽  
Oxygen Precipitation

Effect of Rapid Thermal Annealing on Oxygen Precipitation Behavior in Silicon Wafers

2001 ◽  
Vol 40 (Part 1, No. 5A) ◽  
pp. 3055-3062 ◽  
Author(s):  
Masanori Akatsuka ◽  
Masahiko Okui ◽  
Nobuyuki Morimoto ◽  
Koji Sueoka
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Silicon Wafers ◽  
Precipitation Behavior ◽  
Oxygen Precipitation

scholarly journals The Influence of Wire Speed on Phase Transitions and Residual Stress in Single Crystal Silicon Wafers Sawn by Resin Bonded Diamond Wire Saw

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 429
Author(s):  
Tengyun Liu ◽  
Peiqi Ge ◽  
Wenbo Bi
Keyword(s):  
Residual Stress ◽  
Surface Layer ◽  
Phase Transitions ◽  
Single Crystal ◽  
Amorphous Silicon ◽  
Silicon Wafer ◽  
Single Crystal Silicon ◽  
Silicon Wafers ◽  
Crystal Silicon ◽  
Diamond Wire

Lower warp is required for the single crystal silicon wafers sawn by a fixed diamond wire saw with the thinness of a silicon wafer. The residual stress in the surface layer of the silicon wafer is the primary reason for warp, which is generated by the phase transitions, elastic-plastic deformation, and non-uniform distribution of thermal energy during wire sawing. In this paper, an experiment of multi-wire sawing single crystal silicon is carried out, and the Raman spectra technique is used to detect the phase transitions and residual stress in the surface layer of the silicon wafers. Three different wire speeds are used to study the effect of wire speed on phase transition and residual stress of the silicon wafers. The experimental results indicate that amorphous silicon is generated during resin bonded diamond wire sawing, of which the Raman peaks are at 178.9 cm−1 and 468.5 cm−1. The ratio of the amorphous silicon surface area and the surface area of a single crystal silicon, and the depth of amorphous silicon layer increases with the increasing of wire speed. This indicates that more amorphous silicon is generated. There is both compressive stress and tensile stress on the surface layer of the silicon wafer. The residual tensile stress is between 0 and 200 MPa, and the compressive stress is between 0 and 300 MPa for the experimental results of this paper. Moreover, the residual stress increases with the increase of wire speed, indicating more amorphous silicon generated as well.

Experimental investigation into polishing of monocrystalline silicon wafer using double-disc chemical assisted magnetorheological finishing process

2021 ◽  
pp. 095440622098384
Author(s):  
Mayank Srivastava ◽  
Pulak M Pandey
Keyword(s):  
Surface Roughness ◽  
Silicon Wafer ◽  
Flow Rate ◽  
Silicon Wafers ◽  
Monocrystalline Silicon ◽  
Slurry Flow ◽  
Magnetorheological Finishing ◽  
Finishing Process ◽  
Process Factors ◽  
Slurry Flow Rate

In the present work, a novel hybrid finishing process that combines the two preferred methods in industries, namely, chemical-mechanical polishing (CMP) and magneto-rheological finishing (MRF), has been used to polish monocrystalline silicon wafers. The experiments were carried out on an indigenously developed double-disc chemical assisted magnetorheological finishing (DDCAMRF) experimental setup. The central composite design (CCD) was used to plan the experiments in order to estimate the effect of various process factors, namely polishing speed, slurry flow rate, percentage CIP concentration, and working gap on the surface roughness ([Formula: see text]) by DDCAMRF process. The analysis of variance was carried out to determine and analyze the contribution of significant factors affecting the surface roughness of polished silicon wafer. The statistical investigation revealed that percentage CIP concentration with a contribution of 30.6% has the maximum influence on the process performance followed by working gap (21.4%), slurry flow rate (14.4%), and polishing speed (1.65%). The surface roughness of polished silicon wafers was measured by the 3 D optical profilometer. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) were carried out to understand the surface morphology of polished silicon wafer. It was found that the surface roughness of silicon wafer improved with the increase in polishing speed and slurry flow rate, whereas it was deteriorated with the increase in percentage CIP concentration and working gap.

Oxygen precipitation behavior in heavily arsenic doped silicon crystals

2017 ◽  
Vol 457 ◽  
pp. 325-330 ◽  
Author(s):  
Stephan Haringer ◽  
Daniela Gambaro ◽  
Maria Porrini
Keyword(s):  
Precipitation Behavior ◽  
Silicon Crystals ◽  
Oxygen Precipitation ◽  
Doped Silicon

A Precision Alignment Method to <100> Direction on (110) Silicon Wafer

2001 ◽  
Author(s):  
Fan-Gang Tseng ◽  
Kai-Chen Chang
Keyword(s):  
Silicon Wafer ◽  
Crystal Orientation ◽  
Silicon Wafers ◽  
Innovative Approach ◽  
Alignment Accuracy ◽  
Alignment Method

Abstract This paper proposes a novel pre-etch method to determine the lt;100gt; direction on (110) silicon wafers for bulk etching. Series of circular windows were arranged in an arc of radius 48.9 mm, and bulk-etched to form hexagonal shapes for crystal orientation finding. The corners of the hexagons can be used as an alignment reference for the indication of the lt;100gt; direction on (110) silicon wafers. This innovative approach has been demonstrated experimentally to give an orientation-alignment accuracy of ± 0.03° for (110) wafers with 4-inch diameter.

scholarly journals Backside Chippings Improvement through Wafer Dicing Parameter Optimization and Understanding the Anistropic Silicon Properties

2021 ◽  
pp. 144-152
Author(s):  
Aiza Marie E. Agudon ◽  
Bryan Christian S. Bacquian
Keyword(s):  
Integrated Circuit ◽  
Electronic Devices ◽  
Silicon Wafers ◽  
Form Complex ◽  
Work Related ◽  
Front End ◽  
Wafer Thickness ◽  
Fully Automatic ◽  
Direct Materials ◽  
Selection Of

Semiconductor Companies and Industries soar high as the trend for electronic gadgets and devices increases. Transition from “manual” to “fully automatic” application is one of the advantages why consumer adapt to changes and prefer electronic devices as one of daily answers. Individuals who admire these electronic devices often ask how they are made. As we look inside each device, we can notice interconnected microchips commonly called IC (Integrated Circuit). These are specially prepared silicon wafers where integrated circuit are developed. Commonly, each device is composed of numerous microchips depending on the design and functionality IC production is processed from “front-end” to “back-end” assembly. Front-end assembly includes wafer fabrication where electrical circuitry is prepared and integrated to every single silicon wafers. Back-end assembly covers processing the wafer by cutting into smaller individual and independent components called “dice”. Each dice will be placed into Leadframe, bonded with wires prior encapsulating with mold compounds. After molding, each IC will be cut through a process called singulation. Afterwards, all molded units are subjected for functional testing. Dice is central to each IC; it is where miniature transistor, resistor and capacitor are integrated to form complex small circuitry in microchips. Pre-assembly (Pre-assy) stations have the first hand prior to all succeeding stations. Live wafers are primary direct materials processed in these stations. Robust work instruction and parameter must be practiced during handling and processing to avoid gross rejection and possible work-related defects. The paper is all about the challenges to resolve and improved the backside chippings in 280um wafer thickness in mechanical dicing saw. The conventional Mechanical dicing process induce a lot of mechanical stress and vibration during the cutting process which oftentimes lead to backside chipping and die crack issues. However, backside chippings can mitigate with proper selection of parameter settings and understand the silicon wafer properties.

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