Edge Effects of Nitride Film Patterning on Dislocation Generation in Local Oxidation of Silicon

1998 ◽  
Vol 510 ◽  
Author(s):  
I. V. Peidous ◽  
R. Sundaresan ◽  
E. Quek ◽  
C. K. Lau

AbstractExtensive monitoring of device characteristics in the manufacturing of ULSI with advanced LOCOS isolation revealed the strong dependence of device leakage currents on the process of patterning of silicon nitride films applied as a hard mask for local oxidation of silicon wafers. At the same time, the level of the leakage currents strongly correlated to stress-induced dislocation density in the device structures. Formation of microtrenches on the wafer surface at the nitride film edges was identified to have a major impact on the leakage currents. Surprisingly, structures having nitride film edge profiles with feet were consistently dislocation-free after the local oxidation. This showed that nitride etching process created surface damage that provided effective sites for crystal defect nucleation in silicon at the film edges. Computer simulations demonstrated that the feet at nitride edges substantially suppress stress growth during local oxidation.

1998 ◽  
Vol 532 ◽  
Author(s):  
I. V. Peidous ◽  
R. Sundaresan ◽  
E. Quek ◽  
Y. K. Leung ◽  
M. Beh

ABSTRACTCrystalline quality of locally oxidized silicon wafers has been studied. Wafers from different supply sources were found to be differently susceptible to stress-induced dislocation generation, although they had been produced to the same specification. On the basis of the analysis of a depth distribution of the dislocations, critical resolved shear stress of dislocation movement in the bulk areas of the wafers was determined. It varied from about 1.65 to 5.12 MPa and correlated positively to the surface defect density. The results show that uncontrollable variations of bulk silicon properties may significantly influence the stress-induced defect nucleation on the surface of wafers during processing.


2017 ◽  
Vol 109 ◽  
pp. 750-757
Author(s):  
Lifei Tian ◽  
Guoan Cheng ◽  
Ruiting Zheng ◽  
Kun Tian ◽  
Xiaolu Yan ◽  
...  

2019 ◽  
Vol 963 ◽  
pp. 530-533
Author(s):  
Kevin Moeggenborg ◽  
Ian Manning ◽  
Jon Searson ◽  
Gil Yong Chung

The impact of surface stress due to polish and grind processes on wafer bow was studied as a function of abrasive size. Results indicate that sub-surface damage from these processes can introduce significant surface stress. For polishing processes, this stress is proportional to mean abrasive size. The study also investigates stress as a function of depth below the wafer surface and finds that most stress is concentrated near the wafer surface.


Author(s):  
A.H.W Ngan ◽  
L Zuo ◽  
P.C Wo

Recent experiments indicate that the first yield point of micron-sized metals exhibits significant statistical scatter as well as strong dependence on the specimen size. In this work, molecular dynamics (MD) simulations are carried out to investigate the onset of shear deformation in a small block of material, using an embedded atom potential for the intermetallic Ni 3 Al alloy. Incipient plasticity in the form of homogeneous dislocation generation is observed to occur at atomic sites with interatomic displacements approaching one-half of the Shockley partial Burgers vector. From the distribution function of the interatomic displacements observed in the MD simulations, the probability of a general material volume surviving under given loading conditions is predicted. The survival probability is then calculated for several situations, including homogeneous deformation and nanoindentation, to predict the critical load for incipient plasticity to occur in these situations. The predicted results are compared to micro-pillar compression and nanoindentation experiments on Ni 3 Al available in the literature.


2009 ◽  
Vol 416 ◽  
pp. 529-534 ◽  
Author(s):  
Ren Ke Kang ◽  
Shang Gao ◽  
Zhu Ji Jin ◽  
Dong Ming Guo

With the development of IC manufacturing technology, the machining precision and surface quality of silicon wafer are proposed much higher, but now the planarization techniques of silicon wafer using free abrasive and bonded abrasive have the disadvantage of poor profile accuracy, environmental pollution, deep damage layer, etc. A soft abrasive wheel combining chemical and medical effect was developed in this paper, it could get super smooth, low damage wafer surface by utilizing mechanical friction of abrasives and chemical reaction among abrasives, additives, silicon. A comparison experiment between #3000 soft abrasive wheel and #3000 diamond abrasive wheel was given to study on the grinding performance of soft abrasive wheel. The results showed that: wafer surface roughness ground by soft abrasive wheel was sub-nanometer and its sub-surface damage was only 0.01µm amorphous layer, which were much better than silicon wafer ground by diamond abrasive wheel, but material removal rate and grinding ratio of soft abrasive wheel were lower than diamond wheel. The wafer surface ground by soft abrasive wheel included Ce4+, Ce3+, Si4+, Ca2+ and Si, which indicated that the chemical reaction really occurred during grinding process.


2004 ◽  
Vol 810 ◽  
Author(s):  
A. Satta ◽  
R. Lindsay ◽  
S. Severi ◽  
K. Henson ◽  
K. Maex ◽  
...  

ABSTRACTThe creation of ultra-shallow junction for CMOS devices at the sub-100 nm node is driving significant efforts in developing thermal processing to give rise to high dopant activation in combination with limited diffusion. Flash-assist Rapid Thermal Annealing™ (fRTP™) is a promising new annealing technique, which involves the heating of the bulk of the wafer to an intermediate temperature using rather conventional spike RTP, followed by a short and intense pulse of light localized on the implanted wafer surface.In this work, we have systematically investigated the junction formation of different implants under fRTP anneals in terms of profile and devices. Co-implanted Ge and F species provide more box-like profiles with improved activation. Although leakage currents are higher for fRTP-annealed junctions than for spike-annealed junctions, appropriate fRTP process parameters and correct process conditions provide a critical tool to control and reduce the leakage current of co-implanted fRTP junctions to acceptable levels. Proper implant and anneal are requested for minimizing pattern effect and improving device performance.


2017 ◽  
Vol 897 ◽  
pp. 177-180 ◽  
Author(s):  
Susumu Tsukimoto ◽  
Tatsuhiko Ise ◽  
Genta Maruyama ◽  
Satoshi Hashimoto ◽  
Tsuguo Sakurada ◽  
...  

Evaluation of surface damage layers formed by mechanical grinding processes is indispensable in epi-ready SiC wafer preparation. As well as microstructure, the analysis of local strain distribution in the damage layers gives a clue on control of the wafer quality. Advanced electron backscatter diffraction (EBSD) technique is applied to evaluate the strain distribution of the damage layers. It is revealed that the elastic strain distribution can be classified into a hierarchy of three regions with respect to depth from the surface. Combining EBSD analysis with TEM observation, large compressive elastic strain and misorientation are introduced in the highly-defective region underneath the ground wafer surface. In addition, the gradient distribution of the strain is observed clearly below the highly-defective region. The knowledge of correlating between strain distribution and microstructure is promising to control the damage layer for the wafer preparation.


1990 ◽  
Vol 29 (Part 2, No. 12) ◽  
pp. L2395-L2397 ◽  
Author(s):  
Haruhiro Goto ◽  
Makoto Sasaki ◽  
Tadahiro Ohmi ◽  
Tadashi Shibata ◽  
Atsushi Yamagami ◽  
...  

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