Front-End Integration Effects on Gate Oxide Quality

1996 ◽  
Vol 428 ◽  
Author(s):  
F. Lin ◽  
S. A. Ajuria ◽  
V. Ilderem ◽  
M. P. Masquelier
Keyword(s):  
Electrical Properties ◽  
Low Voltage ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Front End ◽  
Structural And Electrical Properties ◽  
Chemical Usage ◽  
The Impact ◽  
Voltage Breakdown ◽  
Processing Steps

AbstractIn this paper, the impact of several front-end processing steps (up to gate oxidation) on gate oxide integrity (GOI) is evaluated. In PBL isolation processing, the use of as-deposited amorphous silicon (a-Si), subsequently annealed during nitride deposition, results in better structural and electrical properties compared to as-deposited polysilicon or as-deposited a-Si with an extra anneal step prior to nitride deposition. Thicker or dual sacrificial schemes exhibit improved gate oxide low voltage breakdown and charge-to-breakdown. Dilute RCA chemistries during pre-gate cleaning produce equal or better surfaces for gate oxidation than the conventional non-dilute RCA with less chemical usage. As gate oxides are scaled below 100Å, lowering gate oxidation temperature is proven to result in far better gate oxide quality than maintaining process temperatures at or above 900°C and diluting oxygen in either argon or nitrogen.

How Small Is Too Small ? Understanding The Electronic Structure Of Atomic-Scale Transistors

1999 ◽  
Vol 5 (S2) ◽  
pp. 120-121
Author(s):  
D. A. Muller ◽  
T. Sorsch ◽  
S. Moccio ◽  
F. H. Baumann ◽  
K. Evans-Lutterodt ◽  
...  
Keyword(s):  
Electronic Structure ◽  
Electrical Properties ◽  
Thermal Oxidation ◽  
Electronic Devices ◽  
Local Environment ◽  
Gate Oxide ◽  
Atomic Scale ◽  
Gate Oxides ◽  
Bulk Properties ◽  
Commercial Use

The transistors planned for commercial use ten years from now in many electronic devices will have gate lengths shorter than 130 atoms, gate oxides thinner than 1.2 nm of SiO2 and clock speeds in excess of 10 GHz. It is now technologically possible to produce such transistors with gate oxides only 5 silicon atoms thick[l]. Since at least two of those 5 atoms are not in a local environment similar to either bulk Si or bulk SiO2, the properties of the interface are responsible for a significant fraction of the “bulk” properties of the gate oxide. However the physical (and especially their electrical) properties of the interfacial atoms are very different from .bulk Si or bulk SiO2. Further, roughness on an atomic scale can alter the leakage current by orders of magnitude.In our studies of such devices, we found that thermal oxidation tends to produce Si/SiO2 interfaces with 0.1-0.2 nm rms roughness.

Influence of Pre-Gate Cleaning ON Si/SiO2 Interface and Electrical Performance of Cmos Gate Oxide

2000 ◽  
Vol 654 ◽  
Author(s):  
X. Duan ◽  
K. Kisslinger ◽  
L. Mayes ◽  
S. Ruby ◽  
J. Barrett
Keyword(s):  
Electron Microscopy ◽  
Gate Dielectrics ◽  
Gate Oxide ◽  
Atomic Level ◽  
Electrical Performance ◽  
Interface Morphology ◽  
Gate Oxides ◽  
Mos Devices ◽  
Transmission Electron ◽  
The Impact

AbstractThe Si/SiO2 interface is attracting new interest as gate dielectrics in MOS devices become ultra thin. In this paper, the impact of pre-gate cleaning on the morphology of the Si/SiO2 interface and the electrical performance of CMOS gate oxides has been systematically investigated. Using the High-Resolution Transmission Electron Microscopy (HRTEM) technique, we observed the Si/SiO2 interface at an atomic level. We have found a direct experimental relationship between the pre-gate cleaning scheme, Si/SiO2 interface morphology, and the electrical properties of CMOS gate oxides. When the ratio of H2O2:NH4OH ≥ 1.45, the roughness of the Si/SiO2 interface was dramatically improved, which, in turn, increased the Charge-to-Breakdown to an ideal value.

Inversion-Channel MOS Devices for Characterization of 4H-SiC/SiO2 Interfaces

2015 ◽  
Vol 821-823 ◽  
pp. 480-483 ◽  
Author(s):  
A.I. Mikhaylov ◽  
Alexey V. Afanasyev ◽  
V.V. Luchinin ◽  
S.A. Reshanov ◽  
Adolf Schöner ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Gate Oxide ◽  
Process Optimisation ◽  
Gate Oxides ◽  
Mos Structure ◽  
Mos Devices ◽  
Inversion Channel ◽  
And Inversion ◽  
Thermally Grown

Electrical properties of the gate oxides thermally grown in N2O on n-type and p-type 4H-SiC have been compared using conventional MOS structure and inversion-channel MOS structure, respectively. Sufficient difference in the electrical properties of the gate oxides grown on n-type and p-type 4H-SiC was revealed. We conclude that the gate oxide process optimisation using inversion-channel MOS devices is superior as compared to the conventional MOS structure.

Improvement of SiO2/4H-SiC(0001) Interface Properties by H2 and Ar Mixture Gas Treatment Prior to SiO2 Deposition

2018 ◽  
Vol 924 ◽  
pp. 461-464 ◽  
Author(s):  
Hidenori Tsuji ◽  
Takuji Hosoi ◽  
Yutaka Terao ◽  
Takayoshi Shimura ◽  
Heiji Watanabe
Keyword(s):  
High Temperature ◽  
Electrical Properties ◽  
Electron Mobility ◽  
Interface Properties ◽  
Gate Oxides ◽  
Gas Treatment ◽  
The Impact

We investigated the impact of high-temperature H2/Ar mixture gas treatment of 4H-SiC(0001) surfaces before SiO2 deposition on the electrical properties of SiO2/SiC interfaces. Physical characterizations revealed that the SiC surface treated by the H2/Ar mixture gas exhibited a (√3×√3)R30° structure composed of Si-O bonds, indicating that a well-ordered and stable silicate adlayer was formed by the treatment to passivate SiC(0001) surface. Electrical defects at the CVD-grown SiO2/SiC interface was significantly reduced by the treatment. Consequently, a peak electron mobility in SiC-MOSFETs with the deposited gate oxides was enhanced to 24.9 cm2/Vs.

Nitrogen Profile Engineering in Thin Gate Oxides

1998 ◽  
Vol 525 ◽  
Author(s):  
J. Kuehne ◽  
S. Hattangady ◽  
J. Piccirillo ◽  
G. C. Xing ◽  
G. Miner ◽  
...  
Keyword(s):  
Nitric Oxide ◽  
Gate Dielectrics ◽  
Depth Profiling ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Boron Penetration ◽  
Silicon Interface ◽  
Voltage Breakdown

ABSTRACTIn order to prevent boron penetration in PMOS transistors without degrading channel mobility, it is necessary to engineer the distribution of nitrogen introduced into the gate oxide. We have investigated methods of engineering this distribution using nitric oxide (NO) gas in an RTP system to thermally nitride ultra-thin gate oxides. In one approach, the gate oxide is simultaneously grown and nitrided in a mixture of nitric oxide and oxygen. For a 40 Å film, SIMS depth profiling shows that this process moves the nitrogen peak into the bulk of the oxide away from the oxide silicon interface. In another approach, an 11 Å chemical oxide produced by a standard pre-furnace wet clean is nitrided in NO at 800 deg. C. This film is subsequently reoxidized in either oxygen or steam. For an 1100 deg. C., 120 sec RTP reoxidation in oxygen, the final film thickness is 41 Å. The nitrogen has a peak concentration of 5 at. % and the peak is located in the oxide 25 Åfrom the oxide/silicon interface. Ramped voltage breakdown testing was carried out on MOS capacitors built using reoxidized NO nitrided films. They have breakdown characteristics that are equivalent to conventional furnace grown oxides. These films show considerable promise as gate dielectrics for CMOS technologies at geometries of 0.25um and below.

Low-voltage BIMOS AM front-end amplifier

1990 ◽  
Vol 137 (1) ◽  
pp. 57 ◽  
Author(s):  
M. Steyaert ◽  
Z. Chang
Keyword(s):  
Low Voltage ◽  
Front End

Structural and Electrical Properties of Thermally Evaporated SnxSe1-x Thin Films

2011 ◽  
Vol 3 (10) ◽  
pp. 1-4 ◽  
Author(s):  
Bushra A Hasan ◽  
◽  
Ghuson H Mohamed ◽  
Amer A Ramadhan
Keyword(s):  
Thin Films ◽  
Electrical Properties ◽  
Structural And Electrical Properties
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