About the Electrical and Structural Properties of Erbium Thermally Diffused in Single Crystal Silicon

1996 ◽  
Vol 422 ◽  
Author(s):  
S. Binetti ◽  
M. Acciarri ◽  
I. Gelmi ◽  
S. Pizzini
Keyword(s):  
Electrical Properties ◽  
Chemical Analysis ◽  
Silicon Substrate ◽  
Silica Glass ◽  
Single Crystal Silicon ◽  
Auger Spectroscopy ◽  
Erbium Oxide ◽  
Erbium Doping ◽  
Crystal Silicon ◽  
Erbium Doped

AbstractHaving preliminary confirmed the possibility of erbium doping by thermal diffusion, we have used this process to introduce erbium into a silicon substrate from metallic erbium or erbium oxide sources. Diffusion experiments were carried out at 1050, 1200 and 1250°C. The Er:Si diffused samples were investigated using four probe resistivity and thermopower techniques for the measure of the concentration and type of carriers, SIMS and Auger spectroscopy for chemical analysis of the diffused layers and photoluminescence (PL) measurements at temperatures ranging from 2 to 298 K for the detection of optical activity. None of the samples prepared presented measurable PL at 2 K, except for one single sample on top of which was deposited an erbium doped silica glass. The electrical properties, instead, were deeply influenced by doping, indicating the formation of both donor and acceptors.

Electrical Properties of Polycrystalline-Silicon Thin Films for VLSI

1986 ◽  
Vol 71 ◽  
Author(s):  
T I Kamins
Keyword(s):  
Electrical Properties ◽  
Integrated Circuits ◽  
Single Crystal ◽  
Grain Boundaries ◽  
Polycrystalline Silicon ◽  
Crystalline Silicon ◽  
Single Crystal Silicon ◽  
Active Regions ◽  
Crystal Silicon ◽  
Polysilicon Film

AbstractThe electrical properties of polycrystalline silicon differ from those of single-crystal silicon because of the effect of grain boundaries. At low and moderate dopant concentrations, dopant segregation to and carrier trapping at grain boundaries reduces the conductivity of polysilicon markedly compared to that of similarly doped single-crystal silicon. Because the properties of moderately doped polysilicon are limited by grain boundaries, modifying the carrier traps at the grain boundaries by introducing hydrogen to saturate dangling bonds improves the conductivity of polysilicon and allows fabrication of moderate-quality transistors with their active regions in the polycrystalline films. Removing the grain boundaries by melting and recrystallization allows fabrication of high-quality transistors. When polysilicon is used as an interconnecting layer in integrated circuits, its limited conductivity can degrade circuit performance. At high dopant concentrations, the active carrier concentration is limited by the solid solubility of the dopant species in crystalline silicon. The current through oxide grown on polysilicon can be markedly higher than that on oxide of similar thickness grown on singlecrystal silicon because the rough surface of a polysilicon film enhances the local electric field in oxide thermally grown on it. Consequently, the structure must be controlled to obtain reproducible conduction through the oxide. The differences in the behavior of polysilicon and single-crystal silicon and the limited electrical conductivity in polysilicon are having a greater impact on integrated circuits as the feature size decreases and the number of devices on a chip increases in the VLSI era.

TEM of electron-beam induced crystallization of an amorphous AuFe.03/Si Spin-Glass Multilayer

1993 ◽  
Vol 51 ◽  
pp. 1098-1099
Author(s):  
D.A. Howell ◽  
L. Hoines ◽  
M.A. Crimp ◽  
J. Bass ◽  
J.W. Heckman
Keyword(s):  
Thin Film ◽  
Spin Glass ◽  
Cross Sections ◽  
Silicon Substrate ◽  
Giant Magnetoresistance ◽  
Finite Size ◽  
Single Crystal Silicon ◽  
Film Surface ◽  
Glass Slide ◽  
Crystal Silicon

The use of thin film multilayers for the study of physical phenomena (e.g. spin-glass dc magnetic susceptibility, giant magnetoresistance, and x-ray reflectivity) has grown recently as the technology for their preparation has improved. The multilayers in this study were produced for an investigation of finite-size effects in a AuFe.03 spin-glass.We prepared the samples by dc sputtering of a AuFe.03, alloy and a Si target in an UHV system. The specimen in this investigation had 67 bilayers of 3 nm spin-glass layers alternating with 7 nm amorphous silicon (a-Si) layers on a (001) single-crystal silicon substrate for a total film thickness of 670 nm. Ultrathin cross-sections were prepared by cleaning the thin-film surface in Freon TF and gluing this surface to a clean ground-glass slide with epoxy. We removed the thin-film from its silicon substrate by peeling the substrate from the film which remained on the glass slide.

Growth and Characterization of Titanium Nitride Nanowires on Silicon Substrate Using Pulsed Laser Deposition Method for Biological Applications

2013 ◽  
Author(s):  
Seyram Gbordzoe ◽  
K. Mensah-Darkwa ◽  
Ram Gupta ◽  
Dhananjay Kumar
Keyword(s):  
Titanium Nitride ◽  
Pulsed Laser Deposition ◽  
Silicon Substrate ◽  
Laser Energy ◽  
Pulsed Laser ◽  
Single Crystal Silicon ◽  
Laser Deposition ◽  
Sem Images ◽  
Crystal Silicon

The present work reports on the growth and characterization of titanium nitride (TiN) nanowires on silicon substrate using a pulsed laser deposition (PLD) method. The TiN nanowires were grown on single crystal silicon substrate with (100) and (111) orientations at a range of substrate temperatures and under both nitrogen ambient and vacuum. The different orientation of silicon was chosen to see the effect of the substrate orientation on the growth of TiN nanowires. The laser energy entering the vacuum chamber to impinge the TiN target for nanowire deposition was varied from 70 to 80 mJ. The TiN nanowires samples were characterized using Scanning Electron Microscopy (SEM) and X-ray Diffraction (XRD). The diameter of the nanowires was observed to increase from 25 nm to 40 nm with an increase in laser beam energy entering the chamber. The shape and orientation of the nanowires was observed to be the same for (100) and (111) oriented silicon substrates as observed in SEM images. Corrosion tests were also conducted on the TiN nanowires.

Substrate Influence on the Formation of Titanium Silicide on Polycrystalline Silicon

1995 ◽  
Vol 402 ◽  
Author(s):  
Ana Neilde Rodrigues da Silva ◽  
Rogerio Furlan ◽  
J. J. Santiagoaviles
Keyword(s):  
Silicon Substrate ◽  
Polycrystalline Silicon ◽  
Chemical Reactivity ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Titanium Silicide ◽  
Maximum Temperature ◽  
Crystal Silicon ◽  
Kinetics Of Formation ◽  
Sputter Deposited

AbstractIn this work we investigated the influence of the polycrystalline silicon substrate on the titanium silicide formation process. The results are compared to those obtained when single crystal silicon wafers are used. We observed that the polycrystalline substrate affects both the kinetics of formation of the phase TiSi2-C49 and the temperature of transition from TiSi2-C49 to TiSi2-C54. The temperature of this phase transition is also influenced by the presence of phosphorous in the polycrystalline silicon substrate. In order to prevent degradation of the silicide film formed on polycrystalline silicon, the maximum temperature of RTP has to be lower than 900°C. Due to the high chemical reactivity between titanium and oxygen present in the ambient, we also investigated the use of a protective cap. For this purpose, a thin amorphous silicon layer was sputter-deposited sequentially on Ti films without breaking the vacuum.

Fabrication of a Single Crystal Silicon Substrate for AM-LCD Using Vertical Etching of (110) Silicon

1995 ◽  
Vol 377 ◽  
Author(s):  
Jun-Bo Yoon ◽  
Ho-Jun Lee ◽  
Chul-Hi Han ◽  
Choong-Ki Kim
Keyword(s):  
Silicon Substrate ◽  
Crystalline Silicon ◽  
Single Crystal Silicon ◽  
Liquid Crystal Displays ◽  
Ring Oscillator ◽  
Si Substrate ◽  
Crystal Silicon ◽  
Active Matrix ◽  
Single Crystal Silicon Substrate ◽  
Matrix Liquid

ABSTRACTIn this paper, feasibility of crystalline silicon (c-Si) substrate for transmissive active matrix liquid crystal displays (AM-LCDs) has been investigated. The transparent pixel areas of AM-LCD were formed by vertical etching of (110) silicon substrate using anisotropie etching property of aqueous KOH. Combining this vertical etching process with the conventional MOSFET fabrication process, the pixel switching devices, peripheral circuits and transparent apertures were successfully integrated on the same c-Si substrate. The pixel NMOS devices exhibit an electron mobility of about 600cm2/V-s, a subthreshold slope of 65mV/decade and ON/OFF current ratio of 9 decades at 5V drain voltage. And the gate delay time is 3.3ns at 10V power voltage, measured from a ring oscillator which has enhancement-load type NMOS inverters having the (W/L) iload- (W/L) driverer of 25μm/15μm - 50μm/10μm.

scholarly journals Communication—Electrodeposition of Indium Directly on Silicon

2022 ◽  
Author(s):  
Anica Neumann ◽  
Olivia Schneble ◽  
Emily Warren
Keyword(s):  
Single Crystal ◽  
Silicon Substrate ◽  
Low Temperatures ◽  
Seed Layer ◽  
Direct Contact ◽  
Single Crystal Silicon ◽  
Vapor Liquid Solid ◽  
Crystal Silicon ◽  
Single Crystal Silicon Substrate ◽  
Direct Electrodeposition

Abstract Direct electrodeposition of indium onto silicon paves the way for advances in microelectronics, photovoltaics, and optoelectronics. Indium is generally electrodeposited onto silicon utilizing a physically or thermally deposited metallic seed layer. Eliminating this layer poses benefits in microelectronics by reducing resistive interfaces and in vapor-liquid-solid conversion to III-V material by allowing direct contact to the single-crystal silicon substrate for epitaxial conversion. We investigated conditions to directly electrodeposit indium onto n-type Si(100). We show that a two-step galvanostatic plating at low temperatures can consistently produce smooth, continuous films of indium over large areas, in bump morphologies, and conformally into inverted pyramids.

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