Electrical properties of single‐crystal silicon layers formed from polycrystalline silicon by solid phase epitaxy

1981 ◽  
Vol 39 (9) ◽  
pp. 709-711 ◽  
Author(s):  
K. L. Wang ◽  
G. P. Li ◽  
T. W. Sigmon
1986 ◽  
Vol 71 ◽  
Author(s):  
T I Kamins

AbstractThe electrical properties of polycrystalline silicon differ from those of single-crystal silicon because of the effect of grain boundaries. At low and moderate dopant concentrations, dopant segregation to and carrier trapping at grain boundaries reduces the conductivity of polysilicon markedly compared to that of similarly doped single-crystal silicon. Because the properties of moderately doped polysilicon are limited by grain boundaries, modifying the carrier traps at the grain boundaries by introducing hydrogen to saturate dangling bonds improves the conductivity of polysilicon and allows fabrication of moderate-quality transistors with their active regions in the polycrystalline films. Removing the grain boundaries by melting and recrystallization allows fabrication of high-quality transistors. When polysilicon is used as an interconnecting layer in integrated circuits, its limited conductivity can degrade circuit performance. At high dopant concentrations, the active carrier concentration is limited by the solid solubility of the dopant species in crystalline silicon. The current through oxide grown on polysilicon can be markedly higher than that on oxide of similar thickness grown on singlecrystal silicon because the rough surface of a polysilicon film enhances the local electric field in oxide thermally grown on it. Consequently, the structure must be controlled to obtain reproducible conduction through the oxide. The differences in the behavior of polysilicon and single-crystal silicon and the limited electrical conductivity in polysilicon are having a greater impact on integrated circuits as the feature size decreases and the number of devices on a chip increases in the VLSI era.


1990 ◽  
Vol 182 ◽  
Author(s):  
Richard S. Muller

In 1982, Kurt Petersen published “Silicon as a Mechanical Material” in the Proceedings of the IEEE. This thorough review article heightened focus on the advantages of utilizing the mechanical as well as electrical properties of single-crystal silicon. Processes for shaping single-crystal silicon based upon selective etching were shown in the article to make silicon useful for a variety of miniature mechanical devices.


1997 ◽  
Vol 467 ◽  
Author(s):  
N. H. Nickel ◽  
G. B. Anderson ◽  
N. M. Johnson ◽  
J. Walker

ABSTRACTIt is demonstrated that the exposure of polycrystalline silicon (poly-Si) to monatomic hydrogen results in the formation of H clusters. These H stabilized platelets appear in the near-surface region ( 100 nm) and are predominantly oriented along {111} crystallographic planes. Platelet concentrations of ≈5×1015, 1.5×1016-cm−3, and 2.4×1017 cm−3 were observed in nominally undoped poly-Si, phosphorous doped poly-Si (P=1017 cm−3), and phosphorous doped single crystal silicon (P>3×1018 cm−3), respectively. Results obtained on doped c-Si demonstrate that platelet generation occurs only at Fermi-level positions of Ec -EF < 0.4 eV.


1993 ◽  
Vol 301 ◽  
Author(s):  
J. S. Custer ◽  
A. Polman ◽  
E. Snoeks ◽  
G. N. van den Hoven

ABSTRACTSolid phase epitaxy and ion-beam-induced epitaxial crystallization of Er-doped amorphous Si are used to incorporate high concentrations of Er in crystal Si. During solid phase epitaxy, substantial segregation and trapping of Er is observed, with maximum Er concentrations trapped in single crystal Si of up to 2 × 1020 /cm3. Ion-beam-induced regrowth results in very little segregation, with Er concentrations of more than 5 × 1020 /cm3 achievable. Photoluminescence from the incorporated Er is observed.


2000 ◽  
Vol 609 ◽  
Author(s):  
Brian J. Greene ◽  
Joseph Valentino ◽  
Judy L. Hoyt ◽  
James F. Gibbons

ABSTRACTThe fabrication of 250 Å thick, undoped, single crystal silicon on insulator by lateral solid phase epitaxial growth from amorphous silicon on oxide patterned (001) silicon substrates is reported. Amorphous silicon was grown by low pressure chemical vapor deposition at 525°C using disilane. Annealing at temperatures between 540 and 570°C is used to accomplish the lateral epitaxial growth. The process makes use of a Si/Si1-xGex/Si stacked structure and selective etching. The thin Si1-xGex etch stop layer (x=0.2) is deposited in the amorphous phase and crystallized simultaneously with the Si layers. The lateral growth distance of the epitaxial region was 2.5 μm from the substrate seed window. This represents a final lateral to vertical aspect ratio of 100:1 for the single crystal silicon over oxide regions after selective etching of the top sacrificial Si layer. The effects of Ge incorporation on the lateral epitaxial growth process are also discussed. The lateral epitaxial growth rate of 20% Ge alloys is enhanced by roughly a factor of three compared to the rate of Si films at an anneal temperature of 555°C. Increased random nucleation rates associated with Ge alloy films are shown to be an important consideration when employing Si1-xGex to enhance lateral growth or as an etch stop layer.


Sign in / Sign up

Export Citation Format

Share Document