Electrical Transport Mechanisms in p+a-SiC:H/n c-Si Heterojunctions: dark J-V-T Characteristics

1996 ◽  
Vol 420 ◽  
Author(s):  
M. W. M van Cleef ◽  
M. W. H. Philippens ◽  
F. A. Rubinelli ◽  
M. Kolter ◽  
R. E. I. Schropp
Keyword(s):  
Bias Voltage ◽  
Electrical Transport ◽  
Room Temperature ◽  
Crystalline Silicon ◽  
Forward Bias ◽  
Equivalent Circuit Model ◽  
Interface State ◽  
Transport Mechanisms ◽  
Forward Bias Voltage ◽  
State Densities

AbstractIn the present paper we show results of dark current-voltage measurements performed on p+ a- SiC:H/n c-Si heterojunction diodes at various temperatures (100–400K). We investigated the voltage derivative of these J-V curves in order to the distinguish possible current transport mechanisms. It was found that for low temperatures (<300K), the current is determined by recombination of carriers in the crystalline silicon, whereas at high temperature (>300 K), by a tunnelling mechanism. At room temperature, both mechanisms contribute to the current. By using an equivalent circuit model and detailed numerical simulations we have interpreted our experimental characteristics. The simulations done at room temperature, show that at low forward bias voltage the current is controlled by recombination in the crystalline silicon and that at high forward bias voltage by a combination of multi-step tunnelling and a-SiC:H series resistance. For interface state densities equal to or higher than 1012 cm−2, the recombination was found to be dominated by the states at the amorphous-crystalline silicon interface.

Forward bias voltage controlled infrared photodetection and electroluminescence from ap-i-nquantum dot structure

2011 ◽  
Vol 99 (2) ◽  
pp. 023502 ◽  
Author(s):  
Kai Cui ◽  
Wenquan Ma ◽  
Yanhua Zhang ◽  
Jianliang Huang ◽  
Yang Wei ◽  
...  
Keyword(s):  
Bias Voltage ◽  
Forward Bias ◽  
Forward Bias Voltage ◽  
Infrared Photodetection

scholarly journals Electrical Properties of Rapidly Annealed Ir and Ir/Au Schottky Contacts on n-Type InGaN

2012 ◽  
Vol 2012 ◽  
pp. 1-9 ◽  
Author(s):  
V. Rajagopal Reddy ◽  
B. Prasanna Lakshmi ◽  
R. Padma
Keyword(s):  
Barrier Height ◽  
Annealing Temperature ◽  
Schottky Diodes ◽  
Forward Bias ◽  
Interface State ◽  
Schottky Contacts ◽  
Barrier Heights ◽  
Current Voltage ◽  
State Densities ◽  
Optimum Annealing Temperature

The effect of annealing temperature on electrical characteristics of iridium (Ir) and iridium/gold (Ir/Au) Schottky contacts to n-type InGaN have been investigated by means of current-voltage (I-V) and capacitance-voltage (C-V) techniques. It is observed that the barrier height of Ir/n-InGaN and Au/Ir/n-InGaN Schottky diodes increases after annealing at 300∘C for 1 min in N2 ambient compared to the as-deposited. However, the barrier heights are found to be decreased somewhat after annealing at 500∘C for the both Ir and Ir/Au Schottky contacts. From the above observations, it is clear that the optimum annealing temperature for both Ir and Ir/Au Schottky contacts is 300∘C. Moreover, the barrier height (ϕb), ideality factor (n) and series resistance (RS) are determined using Cheung’s and Norde methods. Besides, the energy distribution of interface state densities are determined from the forward bias I-V characteristics by taking into account the bias dependence of the effective barrier height. Based on the above results, it is clear that both Ir and Ir/Au Schottky contacts exhibit a kind of thermal stability during annealing.

Room Temperature Operation of UV-LED Composed of TCO Hetero p-n Junction, p-SrCu2O2/n-ZnO

2000 ◽  
Vol 623 ◽  
Author(s):  
Hiromichi Ohta ◽  
Ken-Ichi Kawamura ◽  
Masahiro Orita ◽  
Nobuhiko Sarukura ◽  
Masahiro Hirano ◽  
...  
Keyword(s):  
Room Temperature ◽  
Uv Light ◽  
Forward Bias ◽  
Photo Luminescence ◽  
State Density ◽  
Turn On ◽  
Forward Bias Voltage ◽  
Uv Led ◽  
The Difference ◽  
Room Temperature Operation

AbstractRoom temperature operation of UV LED is realized for the first time using a hetero p-n junction composed of transparent conductive oxides, p-SrCu2O2 and n-ZnO. Ni/SrCu2O2/ZnO/ITO multi-layered film was epitaxially grown on an extremely flat YSZ (111) surface by a PLD. The grown films were processed by a conventional photolithography, followed by reactive ion etching to fabricate p-n junction diode. The resultant device exhibited rectifying I-V characteristics inherent to p-n junction whose turn-on voltage was about 1.5V. A relatively sharp electro-luminescence band centered at 382nm was generated when applying the forward bias voltage larger than the turn-on voltage of 3V. The red shift in the EL peak was noticed from that of photo-luminescence (377nm), which was most likely due to the difference in the excited state density between the emission processes. The EL band is attributed to transition in ZnO, probably to that associated with electron-hole plasma. The photo-voltage was also generated when the p-n junction was irradiated with UV light of which energy coincided with both exciton and band-to-band transitions in ZnO.

The photocurrent modulation of quantum dot resonant tunneling diode with forward bias voltage

2011 ◽  
Author(s):  
Daming Zhou ◽  
Wangping Wang ◽  
Qianchun Weng ◽  
Ning Li ◽  
Bo Zhang ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Bias Voltage ◽  
Resonant Tunneling ◽  
Forward Bias ◽  
Resonant Tunneling Diode ◽  
Forward Bias Voltage ◽  
Tunneling Diode

Improvement of Luminous Efficiency in White Light Emitting Diodes by Reducing a Forward-bias Voltage

2007 ◽  
Vol 46 (No. 40) ◽  
pp. L963-L965 ◽  
Author(s):  
Yukio Narukawa ◽  
Masahiko Sano ◽  
Masatsugu Ichikawa ◽  
Shunsuke Minato ◽  
Takahiko Sakamoto ◽  
...  
Keyword(s):  
Bias Voltage ◽  
White Light ◽  
Light Emitting Diodes ◽  
Forward Bias ◽  
Luminous Efficiency ◽  
Light Emitting ◽  
Forward Bias Voltage ◽  
White Light Emitting Diodes

Drift Mobility Measurements in Porous Silicon

1996 ◽  
Vol 420 ◽  
Author(s):  
L. Tsybeskov ◽  
C. Peng ◽  
P. M. Fauchet ◽  
Q. Gu ◽  
E. A. Schiff
Keyword(s):  
Porous Silicon ◽  
Response Time ◽  
Room Temperature ◽  
Forward Bias ◽  
Drift Mobility ◽  
Maximum Response ◽  
Forward Bias Voltage ◽  
Maximum Response Time ◽  
Temperature Time ◽  
Applied Forward Bias

AbstractModulated electroluminescence (EL) measurements performed on a series of porous silicon (PSi) diodes are presented. The maximum response time of the devices scales with the square of the PSi layer thickness and inversely with the applied forward bias voltage. These scaling results indicate that the maximum response time is a carrier transit time from which a drift mobility μ of 10−4 cm2/Vs is deduced at room temperature. Time-of-flight transport measurements on PSi are in qualitative agreement with this value for μ in addition, they identify μ as the electron mobility and show that transport is dispersive, in contrast to the interpretation of the modulated EL experiments.

Observation of a Non-stoichiometric Layer at the Silicon Dioxide – Silicon Carbide Interface: Effect of Oxidation Temperature and Post-Oxidation Processing Conditions

2000 ◽  
Vol 640 ◽  
Author(s):  
K. C. Chang ◽  
Q. Wahab ◽  
L. M. Porter
Keyword(s):  
Transition Layer ◽  
Room Temperature ◽  
Oxide Thickness ◽  
Interface State ◽  
Oxidation Temperature ◽  
Oxide Semiconductor ◽  
Processing Conditions ◽  
Annealing Conditions ◽  
State Densities ◽  
Electron Energy Loss

ABSTRACTThermal oxides were grown on n-type 6H-SiC(0001) at 1100 °C for 2 hrs in a wet oxygen ambient after the substrates were cleaned using the complete RCA cleaning process. Metal-oxide-semiconductor (MOS) diodes were then fabricated and subsequently cleaned under different annealing conditions, including re-oxidation-, NO-, and forming gas (10% H2 + 90% N2)-annealing at 950 °C for one hour. Measurements of the interface state densities (Dit) at room temperature showed that post oxidation annealing (POA) reduced the Dit values to a varying degree depending on the specific annealing condition. Annealing in NO and forming gas resulted in the largest reduction in Dit values.Oxides were grown at 950, 1100, and 1250 °C for varying amounts of time without receiving POA. A non-stoichiometric (SixC, x>1) transition layer adjacent to the SiO2/SiC interface has been observed by electron energy loss spectroscopy (EELS). The thickness of this layer was found to increase with oxidation temperature and was not observed at all for a thin oxide grown at 950 °C. The Dit values (close to the conduction band) for diodes with oxides grown at 950°C without POA were lower than the Dit values for the samples oxidized at 1100 °C with any of the POA treatments. While the thickness of the transition layer was found to be dependent on temperature, our results indicate that it is independent of oxide thickness. This transition layer may be associated with the high Dit values and low channel mobilities for SiC MOSFETs.

Electronic Transport Across Porous/Crystalline Silicon Heterojunctions

2002 ◽  
Vol 716 ◽  
Author(s):  
Md. N. Islam ◽  
Sanjay K. Ram ◽  
Satyendra Kumar
Keyword(s):  
Electronic Transport ◽  
Reverse Bias ◽  
Crystalline Silicon ◽  
Forward Bias ◽  
Reverse Current ◽  
Transport Mechanisms ◽  
Carrier Generation ◽  
Diode Ideality Factor ◽  
Tunneling Recombination ◽  
Silicon Heterojunctions

AbstractAl/PS junctions are non-rectifying and quasi-linear whereas Al/PS/c-Si junctions are weakly rectifying. The rectifying behavior is due to PS/c-Si heterojunction. The diode ideality factor (n) is about 8 for bias ≤0.5 V (about 50 for bias ≤5 V) at forward bias and nearly 1 for ≤0.5 V at reverse bias. As the temperature decreases, n at both forward and reverse biases increases. Different current transport mechanisms are found to be operating across the PS/c-Si junctions under forward and reverse biases. The barrier height measured from I-V data for ≤0.5 V is higher for forward bias than that for reverse bias. For high reverse biases (>5 V), the reverse current increases slowly following In(I)∝ V1/2 law. I-V results on PS/c-Si junctions are explained by a multi tunneling-recombination model for forward bias while carrier generation-recombination and barrier lowering effects for reverse bias.

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