A Relationship between Interface Trap Density and Transconductance in 6H-SiC Enhancement Mode Field Effect Transistors

1995 ◽  
Vol 410 ◽  
Author(s):  
M. W. Dryfuse ◽  
M. Tabib-Azar
Keyword(s):  
Experimental Data ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Interface Traps ◽  
Pertinent Literature ◽  
Enhancement Mode ◽  
Mode Field ◽  
Simplifying Assumptions

ABSTRACTAn explicit analytical expression relating the interface trap densities and transconductance is derived for enhancement mode field effect transistors without any simplifying assumptions regarding the energy distribution of traps. Using this relationship, the interface trap densities were calculated from transconductance data and compared to experimental data and that provided in the literature. Our expression provides a simple and convenient method to reliably estimate interface traps densities from the readily available transconductance data provided in the pertinent literature.

scholarly journals Interface trap density and mobility extraction in InGaAs buried quantum well metal-oxide-semiconductor field-effect-transistors by gated Hall method

2014 ◽  
Vol 104 (13) ◽  
pp. 131605 ◽  
Author(s):  
Thenappan Chidambaram ◽  
Dmitry Veksler ◽  
Shailesh Madisetti ◽  
Andrew Greene ◽  
Michael Yakimov ◽  
...  
Keyword(s):  
Quantum Well ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Trap Density ◽  
Oxide Semiconductor ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Hall Method

Enhancement-mode field-effect transistors based on Ti-doped In2O3 nanowires fabricated by electrospinning

2019 ◽  
Vol 52 (22) ◽  
pp. 225102
Author(s):  
Zhuodong Li ◽  
You Meng ◽  
Chao Wang ◽  
Youchao Cui ◽  
Zhao Yao ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Enhancement Mode ◽  
Mode Field

From planar to vertical nanowires field-effect transistors

2012 ◽  
Vol 1439 ◽  
pp. 101-107
Author(s):  
Guillaume Rosaz ◽  
Bassem Salem ◽  
Nicolas Pauc ◽  
Pascal Gentile ◽  
Priyanka Periwal ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
The State ◽  
Hysteretic Behavior ◽  
Interface Trap ◽  
Interface Traps ◽  
Oxide Interface ◽  
Back Gate ◽  
Technological Processes

ABSTRACTThe authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104but with poor dynamics which can be explained by the high interface traps density.

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