From planar to vertical nanowires field-effect transistors

2012 ◽  
Vol 1439 ◽  
pp. 101-107
Author(s):  
Guillaume Rosaz ◽  
Bassem Salem ◽  
Nicolas Pauc ◽  
Pascal Gentile ◽  
Priyanka Periwal ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
The State ◽  
Hysteretic Behavior ◽  
Interface Trap ◽  
Interface Traps ◽  
Oxide Interface ◽  
Back Gate ◽  
Technological Processes

ABSTRACTThe authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104but with poor dynamics which can be explained by the high interface traps density.

ELECTRICAL CHARACTERIZATION OF PLANAR SILICON NANOWIRE FIELD-EFFECT TRANSISTORS

2012 ◽  
Vol 11 (04) ◽  
pp. 1240011
Author(s):  
G. ROSAZ ◽  
B. SALEM ◽  
N. PAUC ◽  
P. GENTILE ◽  
A. POTIÉ ◽  
...  
Keyword(s):  
Silicon Nanowires ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Electrical Characterization ◽  
Hysteretic Behavior ◽  
Oxide Shell ◽  
Back Gate ◽  
Voltage Sweep

Silicon nanowires (Si NWs) are promising candidates for field-effect transistor (FET) conduction channel. Planar configuration using a back gate is an easy way to study these devices. We demonstrate the possibility to build high performance FET using a simple silicidation process leading to high effective holes' mobility between 130 cm2⋅V-1⋅s-1 and 200 cm2⋅V-1⋅s-1 and good ION/IOFF ratio up to 105. Moreover we investigated the possibility to passivate the NWs using either a high-k dielectric layer or a thermal oxide shell around the NWs. This leads to a reduction of the hysteretic behavior during the gate voltage sweep from 30 V to 1 V depending on the material and the gate configuration.

A Relationship between Interface Trap Density and Transconductance in 6H-SiC Enhancement Mode Field Effect Transistors

1995 ◽  
Vol 410 ◽  
Author(s):  
M. W. Dryfuse ◽  
M. Tabib-Azar
Keyword(s):  
Experimental Data ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Interface Traps ◽  
Pertinent Literature ◽  
Enhancement Mode ◽  
Mode Field ◽  
Simplifying Assumptions

ABSTRACTAn explicit analytical expression relating the interface trap densities and transconductance is derived for enhancement mode field effect transistors without any simplifying assumptions regarding the energy distribution of traps. Using this relationship, the interface trap densities were calculated from transconductance data and compared to experimental data and that provided in the literature. Our expression provides a simple and convenient method to reliably estimate interface traps densities from the readily available transconductance data provided in the pertinent literature.

scholarly journals Impact of Interface Traps on Direct and Alternating Current in Tunneling Field-Effect Transistors

2015 ◽  
Vol 2015 ◽  
pp. 1-14
Author(s):  
Zhi Jiang ◽  
Yiqi Zhuang ◽  
Cong Li ◽  
Ping Wang ◽  
Yuqi Liu
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Great Influence ◽  
Peak Shift ◽  
Flat Band ◽  
Interface Traps ◽  
Oxide Interface ◽  
Band Shift ◽  
Simulation Tools ◽  
The Impact

We demonstrate the impact of semiconductor/oxide interface traps (ITs) on the DC and AC characteristics of tunnel field-effect transistors (TFETs). Using the Sentaurus simulation tools, we show the impacts of trap density distribution and trap type on the n-type double gate- (DG-) TFET. The results show that the donor-type and acceptor-type ITs have the great influence on DC characteristic at midgap. Donor-like and acceptor-like ITs have different mechanism of the turn-on characteristics. The flat band shift changes obviously and differently in the AC analysis, which results in contrast of peak shift of Miller capacitorCgdfor n-type TFETs with donor-like and acceptor-like ITs.

scholarly journals Interface trap density and mobility extraction in InGaAs buried quantum well metal-oxide-semiconductor field-effect-transistors by gated Hall method

2014 ◽  
Vol 104 (13) ◽  
pp. 131605 ◽  
Author(s):  
Thenappan Chidambaram ◽  
Dmitry Veksler ◽  
Shailesh Madisetti ◽  
Andrew Greene ◽  
Michael Yakimov ◽  
...  
Keyword(s):  
Quantum Well ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Trap Density ◽  
Oxide Semiconductor ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Hall Method

scholarly journals Templated dewetting of single-crystal sub-millimeter-long nanowires and on-chip silicon circuits

2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Monica Bollani ◽  
Marco Salvalaglio ◽  
Abdennacer Benali ◽  
Mohammed Bouabdellaoui ◽  
Meher Naffouti ◽  
...  
Keyword(s):  
Field Effect ◽  
Large Scale ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
Spontaneous Formation ◽  
Surface Energy Anisotropy ◽  
Energy Anisotropy ◽  
On Chip ◽  
Silicon Based ◽  
Nano Wires

AbstractLarge-scale, defect-free, micro- and nano-circuits with controlled inter-connections represent the nexus between electronic and photonic components. However, their fabrication over large scales often requires demanding procedures that are hardly scalable. Here we synthesize arrays of parallel ultra-long (up to 0.75 mm), monocrystalline, silicon-based nano-wires and complex, connected circuits exploiting low-resolution etching and annealing of thin silicon films on insulator. Phase field simulations reveal that crystal faceting and stabilization of the wires against breaking is due to surface energy anisotropy. Wires splitting, inter-connections and direction are independently managed by engineering the dewetting fronts and exploiting the spontaneous formation of kinks. Finally, we fabricate field-effect transistors with state-of-the-art trans-conductance and electron mobility. Beyond the first experimental evidence of controlled dewetting of patches featuring a record aspect ratio of $$\sim$$~1/60000 and self-assembled $$\sim$$~mm long nano-wires, our method constitutes a distinct and promising approach for the deterministic implementation of atomically-smooth, mono-crystalline electronic and photonic circuits.

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