Detailed Analysis and Computationally Efficient Modeling of Ultra-Shallow Dopant Profiles Obtained by Low Energy B, Bf2, and as Ion Implantation

1995 ◽  
Vol 396 ◽  
Author(s):  
K. B. Parab ◽  
S.-H. Yang ◽  
S. J. Morris ◽  
S. Tian ◽  
M. Morris ◽  
...  

AbstractWith increasing levels of integration, future generations of integrated circuit technology will require extremely shallow dopant profiles. Ion implantation has long been used in semiconductor material processing and will be a vitally important technique for obtaining ultra-shallow dopant profiles. However, implant channeling for low energy ion implantation must be understood and minimized. We report the results of a detailed experimental analysis of 275 ultra-shallow boron, BF2, and arsenic as-implanted profiles, and the development of an accurate and computationally efficient model for ultra-shallow implants.The ultra-shallow dopant profiles have been modeled by using the Dual-Pearson approach, which employs a weighted sum of two Pearson functions to simulate the profiles. The computationally efficient model covers the following range of implant parameters: implant species B, BF2, As; implant energies from 1 keV to 15 keV; any dose; tilt angles from 0° to 10°; all rotation angles (0°-360°). This experimental analysis is important for the development of scaled devices with ultra-shallow junctions, and the computationally efficient model will enable process simulators to predict ultra-shallow as-implanted profiles accurately.

2013 ◽  
Vol 854 ◽  
pp. 141-145
Author(s):  
V.G. Litovchenko ◽  
B. Romanyuk ◽  
O. Oberemok ◽  
V. Popov ◽  
V. Melnik ◽  
...  

Ultra-shallow junctions (USJs) were formed by low-energy As ion implantation with the subsequent furnace annealing. It was found that the significant amount of oxygen is redistributed from the silicon bulk to the arsenic-implanted region. We present the effect of oxygen gettering at the creation of arsenic-doped USJs using the marker layer created by ion implantation of 18O isotope.


1998 ◽  
Vol 532 ◽  
Author(s):  
Ning Yu ◽  
Amitabh Jain ◽  
Doug Mercer

ABSTRACTThe SIA roadmap predicts that junction depths of 500 angstroms are required for CMOS technology nodes of 0.18 μm or beyond by the year 2001. There are several ultra-shallow junction doping techniques currently under investigation. These include beamline ion implantation, plasma immersion ion implantation, and gas immersion laser doping. This study was based on beamline ion implantation of B, P, and As into single-crystal Si wafers at 0.25-2 keV to doses of (2- 10)×1014 at./cm2 with minimized beam energy contamination. Rapid thermal annealing was applied to the implanted wafers at 1000-1050 °C for 10-15 sec at ramp rates of 35- 50 °C/s in a N2 ambient. Transient enhanced diffusion was observed for all three implant species. For example, the depth of 0.25 keV B measured by SIMS increases from 250 to 520 A at a concentration level of l×1017 at./cm3 upon RTA. To minimize the TED, several schemes of defect engineering were applied prior to low energy implantation, including pre-amorphization and implantation of other species. A comparison of TED for different implantation conditions is given with the aim of process development for minimizing TED. The impact of energy contamination on ultra shallow junctions is also addressed.


Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.


Author(s):  
A. I. Ryabchikov ◽  
A. I. Ivanova ◽  
O. S. Korneva ◽  
D. O. Sivin

1986 ◽  
Vol 97 (2) ◽  
pp. K135-K139 ◽  
Author(s):  
J. Bollmann ◽  
H. Klose ◽  
A. Mertens
Keyword(s):  

2008 ◽  
Vol 93 (7) ◽  
pp. 073102 ◽  
Author(s):  
M. C. Salvadori ◽  
M. Cattani ◽  
F. S. Teixeira ◽  
I. G. Brown

2016 ◽  
Vol 30 (4) ◽  
pp. 805-812
Author(s):  
Ting Wang ◽  
Weidong Qian ◽  
Yunfang Fu ◽  
Changlong Cai ◽  
Peihong Mao

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