Modeling Electromigration-Induced Stress Buildup Due to Nonuniform Temperature

1994 ◽  
Vol 338 ◽  
Author(s):  
J. J. Clement ◽  
C. V. Thompson ◽  
A. Enver
Keyword(s):  
Integrated Circuits ◽  
Driving Force ◽  
Stress Evolution ◽  
Nonuniform Temperature ◽  
Flux Divergence ◽  
Atomic Transport ◽  
Atomic Flux ◽  
Induced Stress ◽  
Interconnect Lines ◽  
Stress Buildup

ABSTRACTAtomic transport due to electromigration in interconnect lines in integrated circuits depends strongly on temperature. Therefore temperature nonuniformities can create sites of atomic flux divergence resulting in material accumulation or depletion leading to failure. The mechanical stress which will evolve at the sites of material flux divergence will oppose the electromigration driving force. A model is developed to describe the stress evolution during electromigration in the presence of temperature nonuniformnities. Solutions of the differential equations describing the electromigration-induced stress buildup are calculated numerically. The solutions are compared to experimental data in the literature.

The Effects of the Mechanical Properties of the Confinement Material on Electromigration in Metallic Interconnects

2000 ◽  
Vol 612 ◽  
Author(s):  
Stefan P. Hau-Riege ◽  
Carl V. Thompson
Keyword(s):  
Mechanical Properties ◽  
Integrated Circuits ◽  
Effective Elastic Modulus ◽  
Low Dielectric Constant ◽  
Stress Evolution ◽  
Liner Material ◽  
Low Dielectric ◽  
Aspect Ratios ◽  
Induced Stress ◽  
The Standard Model

AbstractNew low-dielectric-constant inter-level dielectrics are being investigated as alternatives to SiO2 for future integrated circuits. In general, these materials have very different mechanical properties from SiO2. In the standard model, electromigration-induced stress evolution caused by changes in the number of available lattice sites in interconnects is described by an effective elastic modulus, B. Finite element calculations have been carried out to obtain B as a function of differences in the modulus, E, of interlevel dielectrics, for several stress-free homogeneous dilational strain configurations, for several line aspect ratios, and for different metallization schemes. In contradiction to earlier models, we find that for Cu-based metallization schemes with liners, a decrease in E by nearly two orders of magnitude has a relatively small effect on B, changing it by less than a factor of 2. However, B, and therefore the reliability of Cu interconnects can be strongly dependent on the modulus and thickness of the liner material.

The Effects of the Mechanical Properties of the Confinement Material on Electromigration in Metallic Interconnects

2000 ◽  
Vol 15 (8) ◽  
pp. 1797-1802 ◽  
Author(s):  
Stefan P. Hau-Riege ◽  
Carl V. Thompson
Keyword(s):  
Mechanical Properties ◽  
Integrated Circuits ◽  
Effective Elastic Modulus ◽  
Low Dielectric Constant ◽  
Stress Evolution ◽  
Liner Material ◽  
Low Dielectric ◽  
Aspect Ratios ◽  
Induced Stress ◽  
The Standard Model

New low-dielectric-constant interlevel dielectrics are being investigated as alternatives to SiO2 for future integrated circuits. In general, these materials have very different mechanical properties from SiO2. In the standard model, electromigration-induced stress evolution caused by changes in the number of available lattice sites in interconnects is described by an effective elastic modulus, B. Finite element calculations were carried out to obtain B as a function of differences in the modulus, E, of interlevel dielectrics, for several stress-free homogeneous dilational strain configurations, for several line aspect ratios, and for different metallization schemes. In contradiction to earlier models, we found that for Cu-based metallization schemes with liners, a decrease in E by nearly two orders of magnitude has a relatively small effect on B, changing it by less than a factor of 2. However, B, and therefore the reliability of Cu interconnects, can be strongly dependent on the modulus and thickness of the liner material.

Effects of Preexisting Stress Voids on Electromigration Stress Buildup and Flux Divergence

1999 ◽  
Vol 563 ◽  
Author(s):  
Y. -L. Shen ◽  
C. A. Minor ◽  
Y. L. Guo
Keyword(s):  
Stress Field ◽  
Stress Profile ◽  
Flux Divergence ◽  
Element Analysis ◽  
One Dimensional ◽  
Atomic Flux ◽  
The Finite Element Analysis ◽  
The One ◽  
Aluminum Interconnects ◽  
Stress Buildup

AbstractNumerical modeling of electromigration stress buildup and flux divergence was undertaken. The objective is to provide a mechanistic understanding of the question: Do preexisting stress voids grow during later electromigration, to become potentially fatal? Conflicting experimental results have been reported. In this work the stress field in aluminum interconnects containing voids was first quantified using the finite element analysis. The averaged stress field then served as the initial condition in the one-dimensional partial differential equation of electromigration stress buildup. The finite difference method was employed to solve the evolving stress profile and the associated atomic flux and flux divergence along the conducting line. It was found that a large preexisting void suffers greater flux divergence and is therefore more prone to growth during electromigration. A single large stress void is more detrimental than populous small voids. Published experimental observations seem to support these findings.

Comparison of Line Stress Predictions with Measured Electromigration Failure Times

2005 ◽  
Vol 863 ◽  
Author(s):  
Rao R. Morusupalli ◽  
William D. Nix ◽  
Jamshed R. Patel ◽  
Arief S. Budiman
Keyword(s):  
Void Formation ◽  
Atomic Diffusion ◽  
Time To Failure ◽  
Stress Evolution ◽  
Failure Times ◽  
Induced Stress ◽  
Product Lifetime ◽  
Metal Interconnects ◽  
Interconnect Lines ◽  
Pure Cu

AbstractReliability of today's interconnect lines in microelectronic devices is critical to product lifetime. The metal interconnects are carriers of large current densities and mechanical stresses, which can cause void formation or metal extrusion into the passivation leading to failure. The modeling and simulation of stress evolution caused by electromigration in interconnect lines and vias can provide a means for predicting the time to failure of the device. A tool was developed using MathCAD for simulation of electromigration-induced stress in VLSI interconnect structures using a model of electromigration induced stress. This model solves the equations governing atomic diffusion and stress evolution in one dimension. A numerical solution scheme has been implemented to calculate the atomic fluxes and the evolution of mechanical stress in interconnects. The effects of line geometries and overhangs, material properties and electromigration stress conditions have been included in the simulation. The tool has been used to simulate electromigration-induced stress in pure Cu interconnects and a comparison of line stress predictions with measured electromigration failure times is studied. Two basic limiting cases were studied to place some bounds on the results. For a lower bound estimate of the stress it was assumed that the interface can be treated like a grain boundary in Cu. For an upper bound estimate it was assumed that the interface can be treated like a free surface of Cu. Existing data from experimental samples with known structure geometries and electromigration failure times were used to compare the electromigration failure times with predicted stress build-up in the interconnect lines.

Analytical electron microscopy of grain boundaries in Al-Cu metallizations

1992 ◽  
Vol 50 (2) ◽  
pp. 1684-1685
Author(s):  
J. R. Michael ◽  
A. D. Romig ◽  
D. R. Frear
Keyword(s):  
Electron Microscopy ◽  
Integrated Circuits ◽  
Failure Mode ◽  
Current Density ◽  
Thermal History ◽  
Analytical Electron Microscopy ◽  
Cu Metallization ◽  
Analytical Electron ◽  
Interconnect Lines

Al with additions of Cu is commonly used as the conductor metallizations for integrated circuits, the Cu being added since it improves resistance to electromigration failure. As linewidths decrease to submicrometer dimensions, the current density carried by the interconnect increases dramatically and the probability of electromigration failure increases. To increase the robustness of the interconnect lines to this failure mode, an understanding of the mechanism by which Cu improves resistance to electromigration is needed. A number of theories have been proposed to account for role of Cu on electromigration behavior and many of the theories are dependent of the elemental Cu distribution in the interconnect line. However, there is an incomplete understanding of the distribution of Cu within the Al interconnect as a function of thermal history. In order to understand the role of Cu in reducing electromigration failures better, it is important to characterize the Cu distribution within the microstructure of the Al-Cu metallization.

Micromechanics Measurements Applied to Integrated Circuit Microelectronics

1997 ◽  
Vol 473 ◽  
Author(s):  
David R. Clarke
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Fracture Resistance ◽  
Interface Fracture ◽  
New Techniques ◽  
Fracture Properties ◽  
Engineered Structures ◽  
Mechanical And Fracture Properties ◽  
Interconnect Lines ◽  
Metallic Interconnect

ABSTRACTAs in other engineered structures, fracture occasionally occurs in integrated microelectronic circuits. Fracture can take a number of forms including voiding of metallic interconnect lines, decohesion of interfaces, and stress-induced microcracking of thin films. The characteristic feature that distinguishes such fracture phenomena from similar behaviors in other engineered structures is the length scales involved, typically micron and sub-micron. This length scale necessitates new techniques for measuring mechanical and fracture properties. In this work, we describe non-contact optical techniques for probing strains and a microscopic “decohesion” test for measuring interface fracture resistance in integrated circuits.

Variation of Local Mechanical Stress During the Different Processing Steps of Ic-Isolation: a Micro-Raman Spectroscopy Study

1993 ◽  
Vol 308 ◽  
Author(s):  
Ingrid De Wolf ◽  
Herman E. Maes ◽  
Hans Norström
Keyword(s):  
Raman Spectroscopy ◽  
Integrated Circuits ◽  
Mechanical Stress ◽  
Local Variation ◽  
Micro Raman Spectroscopy ◽  
Induced Stress ◽  
Last Stage ◽  
Edge Force ◽  
Field Oxide ◽  
Processing Steps

ABSTRACTLocal mechanical stress introduced in the silicon substrate during the successive steps of poly-buffered local isolation of MOS integrated circuits is studied with micro-Raman spectroscopy. It is shown that the magnitude and the local variation of the stress is highly affected by the different processing steps. After deposition of the nitride mask, the stress can be described as caused by an edge-force. Field oxidation reduces the mask-induced stress but introduces thermal stress from the field oxide. Also the formation of the bird's beak gives rise to additional local tensile stress, especially at the tip of the bird's beak. Removal of the nitride mask results in a partial relaxation: the stress caused by the bird's beak relaxes. In this last stage of the isolation process, the stress image is mostly determined by the field oxide.

scholarly journals Case study on the mining‐induced stress evolution of an extra‐thick coal seam under hard roof conditions

2020 ◽  
Vol 8 (9) ◽  
pp. 3174-3185 ◽  
Author(s):  
Cong Li ◽  
Heping Xie ◽  
Mingzhong Gao ◽  
Jing Xie ◽  
Guangdi Deng ◽  
...  
Keyword(s):  
Coal Seam ◽  
Stress Evolution ◽  
Thick Coal Seam ◽  
Hard Roof ◽  
Induced Stress
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