Combined Simulation and Measurement Study of Temperature Uniformity in Rapid Thermal Processing

1993 ◽  
Vol 303 ◽  
Author(s):  
Yur-Tsai Lin ◽  
Ravi Subrahmanyan ◽  
A. R. Sitaram

ABSTRACTModeling and simulation of rapid thermal processing has been studied extensively in the past. This work presents the results of a combined simulation and measurement study of a commercial multilamp RTP chamber. The simulations were used to estimate the contributions of different geometrical, material, process, and physical effects on temperature uniformity. The physical effects considered in the simulations included radiation, thermal conduction, transient effects during ramp up and cool down and the effects of patterns on the wafer surface. The effects were corroborated by direct temperature measurements using thermocouple embedded wafers, and the results were used to reliably calculate stress effects. The stress distributions were determined analytically in cases without surface films on the wafer. In the case of wafers with surface films, stress distributions were calculated based on thermal strains. This study allows us to concentrate efforts on increasing temperature uniformity to those areas where the greatest benefits in terms of yield and film uniformity can be obtained.

1995 ◽  
Vol 387 ◽  
Author(s):  
Peter Y. Wong ◽  
Ioannis N. Miaoulis ◽  
Cynthia G. Madras

AbstractTemperature measurements and processing uniformity continue to be major issues in Rapid Thermal Processing. Spatial and temporal variations in thermal radiative properties of the wafer surface are sources of non-uniformities and dynamic variations. These effects are due to changes in spectral distribution (wafer or heat source), oxidation, epitaxy, silicidation, and other microstructural transformations. Additionally, other variations are induced by the underlying (before processing) and developing (during processing) patterns on the wafer. Numerical simulations of Co silicidation that account for these factors are conducted to determine the radiative properties, heat transfer dynamics, and resultant processing uniformity.


1991 ◽  
Vol 224 ◽  
Author(s):  
C. Schietinger ◽  
B. Adams ◽  
C. Yarling

AbstractA novel wafer temperature and emissivity measurement technique for rapid thermal processing (RTP) is presented. The ‘Ripple Technique’ takes advantage of heating lamp AC ripple as the signature of the reflected component of the radiation from the wafer surface. This application of Optical Fiber Thermometry (OFT) allows high speed measurement of wafer surface temperatures and emissivities. This ‘Ripple Technique’ is discussed in theoretical and practical terms with wafer data presented. Results of both temperature and emissivity measurements are presented for RTP conditions with bare silicon wafers and filmed wafers.


1996 ◽  
Vol 429 ◽  
Author(s):  
J. C. Thomas ◽  
D. P. Dewitt

AbstractA Monte Carlo model is developed to simulate transient wafer heating as a function of system parameters in a kaleidoscope- or integrating light-pipe type cavity with square cross-section. Trends in wafer temperature uniformity are examined as a function of length-to-width ratio, cavity width, and the number of heating lamps. The effect on temperature determination by a radiometer placed in the bottom end wall of the cavity is simulated.


1987 ◽  
Vol 92 ◽  
Author(s):  
Jim D. Whitfield ◽  
Marie E. Burnham ◽  
Charles J. Varker ◽  
Syd.R. Wilson

The advantages of Silicon-on-Insulator (SO) devices over bulk Silicon devices are well known (speed, radiation hardened, packing density, latch up free CMOS,). In recent years, much effort has been made to form a thin, buried insulating layer just below the active device region. Several approaches are being developed to fabricate such a buried insulating layer. One viable approach is by high dose, high energy oxygen implantation directly into the silicon wafer surface (1-3). With proper implant and annealing conditions, a thin stoichiometric buried oxide with a good crystalline quality silicon overlayer can be formed on which an epitaxial layer can be grown and functional devices and circuits built. As SO1 circuits become market viable, mass production tools and techniques are being developed and evaluated. Of particular interest here is the evaluation of high current oxygen implantation with rapid thermal processing on the electrical characteristics of the oxide-silicon interfaces, the silicon overlayer and the thermally grown oxide on the top surface using measurements on gated diodes and guarded capacitors.


1995 ◽  
Vol 387 ◽  
Author(s):  
Andreas Tillmann

AbstractA new strategy based algorithm to optimize process parameter uniformity (e.g.sheet resistance, oxide thickness) and temperature uniformity on wafers in a commercially available Rapid Thermal Processing (RTP) system with independent lamp control is described. The computational algorithm uses an effective strategy to minimize the standard deviation of the considered parameter distribution. It is based on simulation software which is able to calculate the temperature and resulting parameter distribution on the wafer for a given lamp correction table. A cyclical variation of the correction values of all lamps is done while minimizing the standard deviation of the considered process parameter. After the input of experimentally obtained wafer maps the optimization can be done within a few minutes. This technique is an effective tool for the process engineer to use to quickly optimize the homogeneity of the RTP tool for particular process requirements. The methodology will be shown on the basis of three typical RTP applications (Rapid Thermal Oxidation, Titanium Silicidation and Implant Annealing). The impact of variations of correction values for single lamps on the resulting process uniformity for different applications will be discussed.


1989 ◽  
Vol 146 ◽  
Author(s):  
R. Kakoschek ◽  
E. BuβMann

ABSTRACTA complete theory of wafer heating during rapid thermal processing (RTP) is presented. Excellent agreement with experimental results of two commercial RTP systems is obtained. The temperature uniformity is limited by radiation loss at the wafer edge in the stationary state and by nonuniform illumination of the wafer during ramp-up. Structures on wafers are also potential sources for nonuniform heating. Considerable dynamic temperature inhomogeneities during rap-up might limitfu ture applications of RTPe specially when wafer sizes become larger. Possible improvements are suggested regarding adequate process cycling, chip and equipment design.


Doklady BGUIR ◽  
2020 ◽  
Vol 18 (7) ◽  
pp. 79-86
Author(s):  
J. A. Solovjov ◽  
V. A. Pilipenko ◽  
V. P. Yakovlev

The present work is devoted to determination of the dependence of the heating temperature of the silicon wafer on the lamps power and the heating time during rapid thermal processing using “UBTO 1801” unit by irradiating the wafer backside with an incoherent flow of constant density light. As a result, a mathematical model of silicon wafer temperature variation was developed on the basis of the equation of nonstationary thermal conductivity and known temperature dependencies of the thermophysical properties of silicon and the emissivity of aluminum and silver applied to the planar surface of the silicon wafer. For experimental determination of the numerical parameters of the mathematical model, silicon wafers were heated with light single pulse of constant power to the temperature of one of three phase transitions such as aluminum-silicon eutectic formation, aluminum melting and silver melting. The time of phase transition formation on the wafer surface during rapid thermal processing was fixed by pyrometric method. In accordance with the developed mathematical model, we determined the conversion coefficient of the lamps electric power to the light flux power density with the numerical value of 5.16∙10-3 cm-2 . Increasing the lamps power from 690 to 2740 W leads to an increase in the silicon wafer temperature during rapid thermal processing from 550°to 930°K, respectively. With that, the wafer temperature prediction error in compliance with developed mathematical model makes less than 2.3 %. The work results can be used when developing new procedures of rapid thermal processing for silicon wafers.


1994 ◽  
Vol 342 ◽  
Author(s):  
Andreas Tillmann

ABSTRACTThe modelling of temperature distribution on semiconductor wafers in common RTP-equipment is described. The incident intensity distribution on the wafer is calculated using raytracing. Based on this distribution the temperature distribution on the wafer is determined solving the two-dimensional heat conduction equation. If the dependence of a considered material property on the process temperature is known, the calculated temperature distribution can be convened to a distribution of this parameter.The distinctive feature of the described algorithms is the two-dimensional treatment of the distributions using a grid of ring segments, each with equal area. This grid is identical to the usual circular test patterns of multipoint measurement equipment. This is convenient since the evaluation of temperature uniformity in RTP equipment is done mostly by mapping an appropriate temperature dependent material property. All calculated distributions can be presented by contour plots as well as 3-D plots. This results in a very suitable method to compare simulated and experimental wafer maps.The agreement between simulated and experimental temperature distributions is shown.


1995 ◽  
Vol 389 ◽  
Author(s):  
Andreas Tillmann

ABSTRACTA new strategy based algorithm to optimize process parameter uniformity (e.g. sheet resistance, oxide thickness) and temperature uniformity on wafers in a commercially available Rapid Thermal Processing (RTP) system with independent lamp control is described. The computational algorithm uses an effective strategy to minimize the standard deviation of the considered parameter distribution. It is based on simulation software which is able to calculate the temperature and resulting parameter distribution on the wafer for a given lamp correction table. A cyclical variation of the correction values of all lamps is done while minimizing the standard deviation of the considered process parameter. After the input of experimentally obtained wafer maps the optimization can be done within a few minutes. This technique is an effective tool for the process engineer to use to quickly optimize the homogeneity of the RTP tool for particular process requirements. The methodology will be shown on the basis of three typical RTP applications (Rapid Thermal Oxidation, Titanium Silicidation and Implant Annealing). The impact of variations of correction values for single lamps on the resulting process uniformity for different applications will be discussed.


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