A Review of Silicon-On-Insulator Formation by Oxygen Ion Implantation

1983 ◽  
Vol 27 ◽  
Author(s):  
Russell F. Pinizzotto
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
High Energy ◽  
Silicon On Insulator ◽  
Epitaxial Silicon ◽  
Crystal Silicon ◽  
Buried Oxide ◽  
Soi Technology

ABSTRACTSilicon-on-Insulator structures will be an important technological advance used in future VLSI, VHSIC and threedimensional integrated circuits. The most mature SOI technology other than silicon-on-sapphire is SIMOX, or Separation by Implanted Oxygen. High energy oxygen ions are implanted into single crystal silicon until a stoichiometric buried silicon dioxide layer is formed. After implantation, the material is annealed at high temperature to remove implantation induced defects. The structure is completed by the growth of a thin epitaxial silicon layer. Devices and complex circuits have been successfully fabricated by several research groups. This paper reviews the development of this buried oxide SOI technology from 1973 to 1983. The five major sections discuss the advantages of SOI, the basics of buried oxide formation, the literature published between 1973 and 1983, key issues that must be solved before large scale implementation takes place and, finally, predictions of future developments.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

scholarly journals A Flexible PI/Si/SiO2 Piezoresistive Microcantilever for Trace-Level Detection of Aflatoxin B1

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1118
Author(s):  
Yuan Tian ◽  
Yi Liu ◽  
Yang Wang ◽  
Jia Xu ◽  
Xiaomei Yu
Keyword(s):  
Single Crystal ◽  
Aflatoxin B1 ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Wheatstone Bridge ◽  
Silicon On Insulator ◽  
Passivation Layer ◽  
Spring Constant ◽  
Trace Level ◽  
Crystal Silicon

In this paper, a polyimide (PI)/Si/SiO2-based piezoresistive microcantilever biosensor was developed to achieve a trace level detection for aflatoxin B1. To take advantage of both the high piezoresistance coefficient of single-crystal silicon and the small spring constant of PI, the flexible piezoresistive microcantilever was designed using the buried oxide (BOX) layer of a silicon-on-insulator (SOI) wafer as a bottom passivation layer, the topmost single-crystal silicon layer as a piezoresistor layer, and a thin PI film as a top passivation layer. To obtain higher sensitivity and output voltage stability, four identical piezoresistors, two of which were located in the substrate and two integrated in the microcantilevers, were composed of a quarter-bridge configuration wheatstone bridge. The fabricated PI/Si/SiO2 microcantilever showed good mechanical properties with a spring constant of 21.31 nN/μm and a deflection sensitivity of 3.54 × 10−7 nm−1. The microcantilever biosensor also showed a stable voltage output in the Phosphate Buffered Saline (PBS) buffer with a fluctuation less than 1 μV @ 3 V. By functionalizing anti-aflatoxin B1 on the sensing piezoresistive microcantilever with a biotin avidin system (BAS), a linear aflatoxin B1 detection concentration resulting from 1 ng/mL to 100 ng/mL was obtained, and the toxic molecule detection also showed good specificity. The experimental results indicate that the PI/Si/SiO2 flexible piezoresistive microcantilever biosensor has excellent abilities in trace-level and specific detections of aflatoxin B1 and other biomolecules.

Thermal Conductivity of Ultra Thin Single Crystal Silicon Layers: Part II — Experimental Data and Modeling at High Temperatures

2004 ◽  
Author(s):  
Wenjun Liu ◽  
Mehdi Asheghi ◽  
K. E. Goodson
Keyword(s):  
Experimental Data ◽  
Thermal Conductivity ◽  
Single Crystal ◽  
High Temperatures ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Boltzmann Transport ◽  
Crystal Silicon ◽  
Strained Si

Simulations of the temperature field in Silicon-on-Insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This work presents the first experimental data for 20 and 100 nm thick single crystal silicon layers at high temperatures and develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers. The model applies to temperatures range 300–1000 K for silicon layer thicknesses from 10 nm to 1 μm (and even bulk) and agrees well with the experimental data. In addition, the model has an excellent agreement with the predictions of thin film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation, although it is significantly more robust and convenient for integration into device simulators. The experimental data and predictions are required for accurate thermal simulation of the semiconductor devices, nanostructures and in particular the SOI and strained-Si transistors.

Mechanism for Subambient Interfacial Pressures While Polishing With Liquids

1999 ◽  
Vol 122 (2) ◽  
pp. 450-457 ◽  
Author(s):  
Joseph A. Levert ◽  
Steven Danyluk ◽  
John Tichy
Keyword(s):  
Integrated Circuits ◽  
Contact Stress ◽  
Relative Velocity ◽  
Large Scale ◽  
Single Crystal Silicon ◽  
Leading Edge ◽  
Liquid Viscosity ◽  
Crystal Silicon ◽  
Lower Contact ◽  
Hard Substrates

This paper reports the results of a model for predicting the development of subambient pressures during the polishing of flat hard substrates by sliding against a compliant pad in the presence of a slurry (liquid). This work is an extension of our prior experimental work on the polishing of single crystal silicon wafers with polyurethane pads and high pH slurries containing silica particles. Subambient pressures have important implications in the polishing rate and uniformity of silicon and, therefore, in the manufacture of large-scale integrated circuits. The subambient pressure is the result of pad asperity compression at the wafer leading edge followed by elastic reexpansion beneath the wafer due to the nonuniform wafer/pad contact stress. Liquid is expelled from interasperity voids where high leading edge contact stress causes asperities to be compressed. Lower contact stress behind the leading edge causes asperity reexpansion leading to recreation of interasperity voids and subambient liquid pressures. A Poiseuille like in-flow of liquid from the sides of the wafer limits the value of the subambient pressure. Numerical simulations predict subambient pressures as a function of liquid viscosity and relative velocity of the pad and wafer and the pad and wafer mechanics which follow the same trend as the experimental data. [S0742-4787(00)01702-1]

The Physical and Electrical Properties of Buried Nitride Soi Structures Synthesized By Nitrogen Ion Implantation

1985 ◽  
Vol 53 ◽  
Author(s):  
C. Slawinski ◽  
B.-Y. Mao ◽  
P.-H. Chang ◽  
H.W. Lam ◽  
J.A. Keenan
Keyword(s):  
Ion Implantation ◽  
Nitrogen Concentration ◽  
Silicon Film ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Crystal Silicon ◽  
Nitrogen Ion Implantation ◽  
Donor Formation ◽  
Nitrogen Ion

ABSTRACTBuried nitride silicon-on-insulator (SOI) structures have been fabricated using the technique of nitrogen ion implantation. The crystallinity of the top silicon film was found to be exceptionally good. The minimum channeling yield, Xmin' was better than 3%. This is comparable to the value observed for single crystal silicon. The buried insulator formed during the anneals has been identified as polycrystalline α-Si3 N4 with numerous silicon inclusions. This nitride, however, has been found to remain amorphous in regions at the center of the implant where the nitrogen concentration exceeds the stoichiometric level of Si3N4. Nitrogen donor formation in the top silicon layer has also been observed.

Epitaxial Silicon on Yttria-Stabilized Cubic Zirconia (YSZ) and Subsequent Oxidation of the Si/YSZ Interface

1984 ◽  
Vol 37 ◽  
Author(s):  
L. M. Mercandalli ◽  
D. Pribat ◽  
M. Dupuy ◽  
C. Arnodo ◽  
D. Rondi ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Single Crystal Silicon ◽  
High Energy ◽  
Silicon Films ◽  
Epitaxial Silicon ◽  
Electrical Measurements ◽  
Crystal Silicon ◽  
Transmission Electron ◽  
Microscopy Techniques

Astract(100) single crystal silicon films have been deposited onto (100) oriented Yttria-Stabilized Zirconia (YSZ) substrates by pyrolysis of SiH4 at ∼ 980°C.The as deposited epitaxial silicon films have been characterized by Reflexion High Energy Electron Diffraction and Transmission Electron Microscopy techniques.The as deposited silicon films have also been oxidized by oxygen transport through the substrate, resulting in a Si(100)/ amorphous SiO2/YSZ(100) structure in which the most defective part of the epitaxial silicon deposit has been eliminated. The oxidized interfaces (with SiO2 thicknesses in the 2000 Å range) have then been characterized by Transmission Electron Microscopy in order to assess the improvement in crystalline quality. Electrical measurements have also been performed on MOS-Hall bar structures.

Buried Oxide in Silicon by Oxygen Implantation Into Scanned Wafers

1985 ◽  
Vol 45 ◽  
Author(s):  
A. Mogro-Campero ◽  
R.P. Love ◽  
N. Lewis ◽  
E.L. Hall ◽  
M.D. McConnell
Keyword(s):  
Single Crystal ◽  
Oxygen Concentration ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Temperature Cycling ◽  
Beam Scanning ◽  
Crystal Silicon ◽  
Auger Analysis ◽  
Oxygen Implantation ◽  
Buried Oxide

ABSTRACTA single crystal silicon layer on an insulator is a desirable structure for applications in electronics. One of the leading processes for achieving such a structure is the formation of a buried oxide layer in silicon by heavy dose oxygen implantation. Characteristics of this material have been reported for implantation by beam scanning. In this work we report on material prepared by wafer scanning at rates such that significant temperature cycling occurs during implantation, and we use TEM and Auger analysis to investigate the differences between these samples and others prepared by the conventional technique of beam scanning. For the implantation and annealing conditions used here, we find more oxygen in the top silicon layer in the case of wafer scanning, and the oxygen concentration increases after annealing at 1150°C for 2 hours, leading to a structure of precipitates throughout the single crystal top silicon layer. For beam scanning, the oxygen concentration decreases after annealing and achieves background levels near the surface, leading to a zone which is free of precipitates.

Thin-Film Transistors in CO2-Laser Crystallized Silicon Films On Fused Silica

1982 ◽  
Vol 13 ◽  
Author(s):  
N. M. Johnson ◽  
H. C. Tuan ◽  
M. D. Moyer ◽  
M. J. Thompson ◽  
D. K. Biegelsen ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Fused Silica ◽  
Silicon Films ◽  
Silicon On Insulator ◽  
Bulk Glass ◽  
Crystal Silicon ◽  
Glass Substrates

ABSTRACTThin-film transistors (TFT) have been fabricated in scanned CO2 laser-crystallized silicon films on bulk fused silica. In n-channel enhancement-mode transistors, it is demonstrated that an excessively large leakage current can be electric-field modulated with a gate electrode located beneath the silicon layer. This dual-gate configuration provides direct verification on bulk glass substrates of back-channel leakage as has recently been demonstrated for beam-crystallized silicon films on thermal oxides over silicon wafers. With the application of deep-channel ion implantation to suppress back-channel leakage, high-peformance TFTs have been fabricated in single-crystal silicon films on fused silica. The results demonstrate that scanned CO 2 laser processing of silicon films on bulk glass can provide the basis for a silicon-on-insulator technology.

Pattern buried oxide in silicon-on-insulator-based fabrication of floppy single-crystal-silicon cantilevers

2011 ◽  
Vol 6 (4) ◽  
pp. 240
Author(s):  
Yong Liu ◽  
Gang Zhao ◽  
Baoqing Li ◽  
Li Wen ◽  
Jiaru Chu
Keyword(s):  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon On Insulator ◽  
Crystal Silicon ◽  
Buried Oxide

Thermal Conductivity Measurements of Ultra-Thin Single Crystal Silicon Layers

2005 ◽  
Vol 128 (1) ◽  
pp. 75-83 ◽  
Author(s):  
Wenjun Liu ◽  
Mehdi Asheghi
Keyword(s):  
Thermal Conductivity ◽  
Single Crystal ◽  
Data Storage ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Thermal Engineering ◽  
Boltzmann Transport ◽  
Crystal Silicon ◽  
Strained Si

Self-heating in deep submicron transistors (e.g., silicon-on-insulator and strained-Si) and thermal engineering of many nanoscale devices such as nanocalorimeters and high-density thermomechanical data storage are strongly influenced by thermal conduction in ultra-thin silicon layers. The lateral thermal conductivity of single-crystal silicon layers of thicknesses 20 and 100nm at temperatures between 30 and 450K are measured using joule heating and electrical-resistance thermometry in suspended microfabricated structures. In general, a large reduction in thermal conductivity resulting from phonon-boundary scattering is observed. Thermal conductivity of the 20nm thick silicon layer at room temperature is nearly 22Wm−1K−1, compared to the bulk value, 148Wm−1K−1. The predictions of the classical thermal conductivity theory that accounts for the reduced phonon mean free paths based on a solution of the Boltzmann transport equation along a layer agrees well with the experimental results.

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