Mechanism for Subambient Interfacial Pressures While Polishing With Liquids

1999 ◽  
Vol 122 (2) ◽  
pp. 450-457 ◽  
Author(s):  
Joseph A. Levert ◽  
Steven Danyluk ◽  
John Tichy
Keyword(s):  
Integrated Circuits ◽  
Contact Stress ◽  
Relative Velocity ◽  
Large Scale ◽  
Single Crystal Silicon ◽  
Leading Edge ◽  
Liquid Viscosity ◽  
Crystal Silicon ◽  
Lower Contact ◽  
Hard Substrates

This paper reports the results of a model for predicting the development of subambient pressures during the polishing of flat hard substrates by sliding against a compliant pad in the presence of a slurry (liquid). This work is an extension of our prior experimental work on the polishing of single crystal silicon wafers with polyurethane pads and high pH slurries containing silica particles. Subambient pressures have important implications in the polishing rate and uniformity of silicon and, therefore, in the manufacture of large-scale integrated circuits. The subambient pressure is the result of pad asperity compression at the wafer leading edge followed by elastic reexpansion beneath the wafer due to the nonuniform wafer/pad contact stress. Liquid is expelled from interasperity voids where high leading edge contact stress causes asperities to be compressed. Lower contact stress behind the leading edge causes asperity reexpansion leading to recreation of interasperity voids and subambient liquid pressures. A Poiseuille like in-flow of liquid from the sides of the wafer limits the value of the subambient pressure. Numerical simulations predict subambient pressures as a function of liquid viscosity and relative velocity of the pad and wafer and the pad and wafer mechanics which follow the same trend as the experimental data. [S0742-4787(00)01702-1]

A Review of Silicon-On-Insulator Formation by Oxygen Ion Implantation

1983 ◽  
Vol 27 ◽  
Author(s):  
Russell F. Pinizzotto
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
High Energy ◽  
Silicon On Insulator ◽  
Epitaxial Silicon ◽  
Crystal Silicon ◽  
Buried Oxide ◽  
Soi Technology

ABSTRACTSilicon-on-Insulator structures will be an important technological advance used in future VLSI, VHSIC and threedimensional integrated circuits. The most mature SOI technology other than silicon-on-sapphire is SIMOX, or Separation by Implanted Oxygen. High energy oxygen ions are implanted into single crystal silicon until a stoichiometric buried silicon dioxide layer is formed. After implantation, the material is annealed at high temperature to remove implantation induced defects. The structure is completed by the growth of a thin epitaxial silicon layer. Devices and complex circuits have been successfully fabricated by several research groups. This paper reviews the development of this buried oxide SOI technology from 1973 to 1983. The five major sections discuss the advantages of SOI, the basics of buried oxide formation, the literature published between 1973 and 1983, key issues that must be solved before large scale implementation takes place and, finally, predictions of future developments.

Electrical Properties of Polycrystalline-Silicon Thin Films for VLSI

1986 ◽  
Vol 71 ◽  
Author(s):  
T I Kamins
Keyword(s):  
Electrical Properties ◽  
Integrated Circuits ◽  
Single Crystal ◽  
Grain Boundaries ◽  
Polycrystalline Silicon ◽  
Crystalline Silicon ◽  
Single Crystal Silicon ◽  
Active Regions ◽  
Crystal Silicon ◽  
Polysilicon Film

AbstractThe electrical properties of polycrystalline silicon differ from those of single-crystal silicon because of the effect of grain boundaries. At low and moderate dopant concentrations, dopant segregation to and carrier trapping at grain boundaries reduces the conductivity of polysilicon markedly compared to that of similarly doped single-crystal silicon. Because the properties of moderately doped polysilicon are limited by grain boundaries, modifying the carrier traps at the grain boundaries by introducing hydrogen to saturate dangling bonds improves the conductivity of polysilicon and allows fabrication of moderate-quality transistors with their active regions in the polycrystalline films. Removing the grain boundaries by melting and recrystallization allows fabrication of high-quality transistors. When polysilicon is used as an interconnecting layer in integrated circuits, its limited conductivity can degrade circuit performance. At high dopant concentrations, the active carrier concentration is limited by the solid solubility of the dopant species in crystalline silicon. The current through oxide grown on polysilicon can be markedly higher than that on oxide of similar thickness grown on singlecrystal silicon because the rough surface of a polysilicon film enhances the local electric field in oxide thermally grown on it. Consequently, the structure must be controlled to obtain reproducible conduction through the oxide. The differences in the behavior of polysilicon and single-crystal silicon and the limited electrical conductivity in polysilicon are having a greater impact on integrated circuits as the feature size decreases and the number of devices on a chip increases in the VLSI era.

Mechanisms of Inelastic Deformation and Stress Relaxation in Thin Metallizations Bonded to Hard Substrates

1991 ◽  
Vol 226 ◽  
Author(s):  
M.A. Korhonen ◽  
P. Bergesen ◽  
Che-Yu Li
Keyword(s):  
Thin Films ◽  
Stress Relaxation ◽  
Integrated Circuits ◽  
Large Scale ◽  
Effective Means ◽  
Grain Boundary Sliding ◽  
Dislocation Creep ◽  
Dislocation Glide ◽  
Constrained Deformation ◽  
Hard Substrates

AbstractThe yield strength of metallic thin films bonded to hard substrates can be significantly higher than is customary for bulk samples of the same metal. This is related to the constrained nature of the deformation. The constrained deformation, as well as the commonly observed crystallographic texture of thin films, places restrictive conditions on the mechanisms of deformation that produce stress relaxation. In narrow aluminum based metallizations used as interconnects in large scale integrated circuits thermal stress induced voiding provides an effective means for stress relaxation. For these interconnects, the stress state is tensile after excursions to higher temperatures; the stresses relax mainly by dislocation glide and grain boundary sliding during the cooldown, while the longer term relaxation is governed by stress-induced voiding and dislocation creep.

scholarly journals Strategies for High-Performance Large-Area Perovskite Solar Cells toward Commercialization

Crystals ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 295
Author(s):  
Tianzhao Dai ◽  
Qiaojun Cao ◽  
Lifeng Yang ◽  
Mahmoud Aldamasy ◽  
Meng Li ◽  
...  
Keyword(s):  
Solar Cells ◽  
High Performance ◽  
Large Scale ◽  
High Efficiency ◽  
Perovskite Solar Cells ◽  
Growth Control ◽  
Single Crystal Silicon ◽  
Large Area ◽  
Crystal Silicon ◽  
Control Interface

Perovskite solar cells (PSCs) have received a great deal of attention in the science and technology field due to their outstanding power conversion efficiency (PCE), which increased rapidly from 3.9% to 25.5% in less than a decade, comparable to single crystal silicon solar cells. In the past ten years, much progress has been made, e.g. impressive ideas and advanced technologies have been proposed to enlarge PSC efficiency and stability. However, this outstanding progress has always been referred to as small-area (<0.1 cm2) PSCs. Little attention has been paid to the preparation processes and their micro-mechanisms for large-area (>1 cm2) PSCs. Meanwhile, scaling up is an inevitable way for large-scale application of PSCs. Therefore, we firstly summarize the current achievements for high efficiency and stability large-area perovskite solar cells, including precursor composition, deposition, growth control, interface engineering, packaging technology, etc. Then we include a brief discussion and outlook for the future development of large-area PSCs in commercialization.

scholarly journals Influence of laser nanostructured diamond tools on the cutting behavior of silicon by molecular dynamics simulation

RSC Advances ◽  
2017 ◽  
Vol 7 (25) ◽  
pp. 15596-15612 ◽  
Author(s):  
Houfu Dai ◽  
Genyu Chen ◽  
Shaobo Li ◽  
Qihong Fang ◽  
Bang Hu
Keyword(s):  
Molecular Dynamics ◽  
Molecular Dynamics Simulation ◽  
Large Scale ◽  
Diamond Tool ◽  
Single Crystal Silicon ◽  
Dynamics Simulation ◽  
Crystal Silicon ◽  
Nanometric Cutting ◽  
Dynamics Simulations ◽  
Cutting Behavior

In this study, a series of large-scale molecular dynamics simulations have been performed to study the nanometric cutting of single crystal silicon with a laser-fabricated nanostructured diamond tool.

Mechanisms of Inelastic Deformation and Stress Relaxation in Thin Metallizations Bonded to Hard Substrates

1991 ◽  
Vol 225 ◽  
Author(s):  
M. A. Korhonen ◽  
P. Brørgesen ◽  
Che-Yu Li
Keyword(s):  
Thin Films ◽  
Stress Relaxation ◽  
Integrated Circuits ◽  
Large Scale ◽  
Effective Means ◽  
Grain Boundary Sliding ◽  
Dislocation Creep ◽  
Dislocation Glide ◽  
Constrained Deformation ◽  
Hard Substrates

ABSTRACTThe yield strength of metallic thin films bonded to hard substrates can be significantly higher than is customary for bulk samples of the same metal. This is related to the constrained nature of the deformation. The constrained deformation, as well as the commonly observed crystallographic texture of thin films, places restrictive conditions on the mechanisms of deformation that produce stress relaxation. In narrow aluminum based metallizations used as interconnects in large scale integrated circuits thermal stress induced voiding provides an effective means for stress relaxation. For these interconnects, the stress state is tensile after excursions to higher temperatures; the stresses relax mainly by dislocation glide and grain boundary sliding during the cooldown, while the longer term relaxation is governed by stress-induced voiding and dislocation creep.

CuInSe2 Thin Film Modules for Utility Applications

1994 ◽  
Vol 116 (1) ◽  
pp. 25-27
Author(s):  
C. Fredric ◽  
D. Tarrant ◽  
C. Jensen ◽  
J. Hummel ◽  
J. Ermer
Keyword(s):  
Thin Film ◽  
Large Scale ◽  
Low Cost ◽  
Single Crystal Silicon ◽  
Outdoor Exposure ◽  
Production Costs ◽  
Scale Production ◽  
Large Area ◽  
Crystal Silicon ◽  
Thin Film Fabrication

Recent advances in the efficiency and manufacturing technology of CuInSe2 (CIS) thin films demonstrate the opportunity for low-cost large-scale production of photovoltaics for utility applications. Large area (0.4 m2) submodules with 9.7 percent aperture efficiencies yielding 37.8 watts have been fabricated. Thin film fabrication techniques used in the production of modules enable reduced production costs compared with those for single crystal silicon. The performance of 0.4 m2 modules is projected to exceed 50 watts, based on performance achieved to date on 0.1 m2 modules and small area test devices. Preliminary tests packaged (encapsulated and framed) modules show no significant losses after 15 1/2 months of continuous outdoor exposure. Fabrication of 0.4 m2 modules to demonstrate the feasibility of large-scale commercialization of CIS thin film photovoltaics for utility applications is currently under way.

scholarly journals Research on Silicon Wafer Manufacturing Process and Physical Properties Testing Using High-Purity Polysilicon

2021 ◽  
Vol 2083 (2) ◽  
pp. 022050
Author(s):  
Xiaoming Hu
Keyword(s):  
Integrated Circuits ◽  
Single Crystal ◽  
Silicon Wafer ◽  
High Purity ◽  
Semiconductor Industry ◽  
Single Crystal Silicon ◽  
Process Technology ◽  
Crystal Silicon ◽  
Silicon Ingot ◽  
Correct Orientation

Abstract The shape of a bare wafer is round, so it is called a wafer or a silicon wafer. It is the basis for the production of silicon semiconductor integrated circuits. The silicon wafer is cut from a large piece of semiconductor material silicon ingot. The high-purity polysilicon (its purity is up to 99.999999999%) is into a large single crystal, given the correct orientation and an appropriate amount of N-type or P-type doping, a silicon ingot is obtained through five-step crystal growth. Wafers (wafers) are then made from silicon ingots by more than eight processes. This paper investigates the single crystal silicon growth and wafer preparation process technology, and finally discusses the evolution of wafer size growth and changes in the development of the semiconductor industry chain.

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