The Effects of Iron Contamination on Thin Oxide Breakdown -Experimental and Modeling

1992 ◽  
Vol 262 ◽  
Author(s):  
Worth B. Henley ◽  
Lubek Jastrzebski ◽  
Nadim F. Haddad
Keyword(s):  
Diffusion Length ◽  
Failure Mechanisms ◽  
Iron Concentration ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Surface Photovoltage ◽  
Oxide Breakdown ◽  
Iron Contamination ◽  
Electrical Modelling ◽  
Technique Failure

ABSTRACTThe effect of iron contamination in silicon on the properties of thermally grown thin oxides is studied through electrical modelling and experimental MOSDOT testing. Iron concentration is measured using a surface photovoltage / diffusion length technique. Failure mechanisms related to iron contamination are proposed. Contamination limits for various gate oxide thicknesses are defined. Experimental results show that reduction of oxide thickness from 20nm to lOnm requires a reduction in iron conntamination by 100 times.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology

2013 ◽  
Vol 10 (4) ◽  
pp. 150-154 ◽  
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Leakage Currents ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Operation Temperature

It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

Surface Photovoltage Measurement of Minority Carrier Diffusion Lengths Exceeding Wafer Thickness: Application to Iron Monitoring with Part Per Quadrillion Sensitivity

1993 ◽  
Vol 324 ◽  
Author(s):  
A.M. Kontkiewicz ◽  
J. Lagowski ◽  
M. Dexter ◽  
P. Edelman
Keyword(s):  
Minority Carrier ◽  
Diffusion Length ◽  
Iron Concentration ◽  
Wavelength Dependence ◽  
Surface Photovoltage ◽  
Minority Carrier Diffusion Length ◽  
Carrier Diffusion ◽  
Wafer Thickness ◽  
L Value ◽  
Silicon Based

AbstractWe discuss an approach to iron concentration determination in silicon, based on wafer-scale surface photovoltage measurement of the minority carrier diffusion length in the millimeter range. The approach combines two novel aspects: it overcomes the diffusion length to wafer thickness ratio limitation of previous SPV methods, and it employs iron separation from other recombination centers using rapid photo-dissociation of iron-boron pairs. The wafer thickness limitation was eliminated by using the correct theoretical SPV wavelength dependence instead of simplified asymptotic diffusion length form adopted in all previous treatments and valid only for diffusion lengths much shorter than the wafer thickness. Photo-dissociation of Fe-B pairs and measurement of the corresponding decrease of the L value (caused by creation of iron intersticials) enables iron detection in typical silicon wafers in times of seconds with a sensitivity in the low 108 atoms/cm3 range.

Relation between Defects on 4H-SiC Epitaxial Surface and Gate Oxide Reliability

2013 ◽  
Vol 740-742 ◽  
pp. 745-748 ◽  
Author(s):  
J. Sameshima ◽  
Osamu Ishiyama ◽  
Atsushi Shimozato ◽  
K. Tamura ◽  
H. Oshima ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Wafer Surface ◽  
Cross Sectional ◽  
Mos Capacitors ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Breakdown Region

Time-dependent dielectric breakdown (TDDB) measurement of MOS capacitors on an n-type 4 ° off-axis 4H-SiC(0001) wafer free from step-bunching showed specific breakdown in the Weibull distribution plots. By observing the as-grown SiC-epi wafer surface, two kinds of epitaxial surface defect, Trapezoid-shape and Bar-shape defects, were confirmed with confocal microscope. Charge to breakdown (Qbd) of MOS capacitors including an upstream line of these defects is almost the same value as that of a Wear-out breakdown region. On the other hand, the gate oxide breakdown of MOS capacitors occurred at a downstream line. It has revealed that specific part of these defects causes degradation of oxide reliability. Cross-sectional TEM images of MOS structure show that gate oxide thickness of MOS capacitor is non-uniform on the downstream line. Moreover, AFM observation of as-grown and oxidized SiC-epitaxial surfaces indicated that surface roughness of downstream line becomes 3-4 times larger than the as-grown one by oxidation process.

Non-Contact Mapping of Fe Contamination in Oxidized Si Wafers with Sensitivity in Part-Per-Trillion Range

1996 ◽  
Vol 428 ◽  
Author(s):  
Jacek Lagowski ◽  
Piotr Edelman
Keyword(s):  
Minority Carrier ◽  
Diffusion Length ◽  
Gate Oxide ◽  
Atom Fraction ◽  
Minority Carrier Diffusion Length ◽  
Contact Mapping ◽  
The Past ◽  
Recombination Efficiency ◽  
Iron Contamination ◽  
Before And After

AbstractTraces of iron contamination as minute as one part per trillion atom fraction can be detrimental to the gate oxide integrity of the very thin oxides, 10 nm or less, used in the most advanced ICs. Fe contamination monitoring discussed in this paper is done with the surface photovoltage (SPV) technique which measures the minority carrier diffusion length, L, before and after the recombination efficiency of iron is enhanced by optical splitting of the iron-boron pairs. Wafer-scale mapping of iron gives fingerprints of contaminating tools and processes. In this paper, we also present an extension of SPV to oxidized wafers. In the past, such measurements were rendered impossible due to optical interference in the SiO2.The apparatus incorporates a whole wafer, optical Fe activation station and it provides whole wafer maps of Fe in a total time of 6 to 20 minutes per wafer, depending on probing density.

The Effect of Roughness Features on Mos Surface Electric Field and Fowler-Nordheim Tunneling Behavior

1997 ◽  
Vol 473 ◽  
Author(s):  
Heng-Chih Lin ◽  
Edwin C. Kan ◽  
Toshiaki Yamanaka ◽  
Simon J. Fang ◽  
Kwame N. Eason ◽  
...  
Keyword(s):  
Electric Field ◽  
Three Dimensional ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Interface Roughness ◽  
Normal Electric Field ◽  
Surface Electric Field ◽  
Tunneling Behavior ◽  
Nordheim Tunneling

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

A Study of Pad Contamination Defect and Removal

2008 ◽  
Author(s):  
K.A. Mohammad ◽  
L.J. Liu ◽  
S.F. Liew ◽  
S.F. Chong ◽  
D.G. Lee ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Oxide ◽  
Action Plans ◽  
Preventive Action ◽  
Oxide Breakdown ◽  
Reliability Level ◽  
The Future ◽  
Dry Etch ◽  
Removal Technique

Abstract The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.

Sign in / Sign up

Export Citation Format

Share Document