Surface photovoltage analysis of iron contamination in silicon processing and the relation to gate oxide integrity

1995 ◽  
Author(s):  
Worth B. Henley
Keyword(s):  
Gate Oxide ◽  
Surface Photovoltage ◽  
Iron Contamination ◽  
Gate Oxide Integrity

The Effects of Iron Contamination on Thin Oxide Breakdown -Experimental and Modeling

1992 ◽  
Vol 262 ◽  
Author(s):  
Worth B. Henley ◽  
Lubek Jastrzebski ◽  
Nadim F. Haddad
Keyword(s):  
Diffusion Length ◽  
Failure Mechanisms ◽  
Iron Concentration ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Surface Photovoltage ◽  
Oxide Breakdown ◽  
Iron Contamination ◽  
Electrical Modelling ◽  
Technique Failure

ABSTRACTThe effect of iron contamination in silicon on the properties of thermally grown thin oxides is studied through electrical modelling and experimental MOSDOT testing. Iron concentration is measured using a surface photovoltage / diffusion length technique. Failure mechanisms related to iron contamination are proposed. Contamination limits for various gate oxide thicknesses are defined. Experimental results show that reduction of oxide thickness from 20nm to lOnm requires a reduction in iron conntamination by 100 times.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Materials, device and gate oxide integrity evaluation of SIMOX and bonded SOI wafers

2002 ◽  
Author(s):  
S.R. Wilson ◽  
T. Wetteroth ◽  
S. Hong ◽  
H. Shin ◽  
B.-Y. Hwang ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Gate Oxide Integrity

Gate oxide integrity on ITOX-SIMOX substrates and influence of test device geometry on characterization

2001 ◽  
Vol 48 (2) ◽  
pp. 307-315 ◽  
Author(s):  
K. Kawamura ◽  
H. Deai ◽  
H. Sakamoto ◽  
T. Yano ◽  
I. Hamaguchi ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Test Device ◽  
Device Geometry ◽  
Gate Oxide Integrity
Sign in / Sign up

Export Citation Format

Share Document