Electron and Hole Transport in a-SiH at High Field and Low Temperature

1992 ◽  
Vol 258 ◽  
Author(s):  
C. E. Nebel ◽  
R. A. Street
Keyword(s):  
Electron Transport ◽  
Low Temperature ◽  
Field Effect ◽  
High Field ◽  
Hole Transport ◽  
Space Charge Limited Current ◽  
Band Tail ◽  
Tail State ◽  
Current Decay ◽  
Enhanced Conductivity

ABSTRACTLow temperature, high field properties of electron and hole transport are investigated by time-of-flight (TOF), steady-state and transient space charge limited current (SCLC) experiments on intrinsic a-Si:H. Charge collection and TOF experiments performed at T= 80 K reveal hole μτ-products of = 8 × 10-10 cm2/V and hole mobilities μ ≤ 9×10-3 cm2/Vs. The field effect on hole thermalization is demonstrated by evaluation of the post transit current decay. SCLC experiments on p+ -i-n+ (electron transport) and p + -i-n+ (hole transport) configurations are introduced and interpreted in terms of field enhanced conductivity and mobility. The experiments demonstrate the overwhelming field effect on carrier hopping in the band tail regions of a-Si:H. Considerably higher fields have to be applied in the case of hole transport than electron transport to achieve comparable conductivities; this is discussed on the basis of the different tail state distributions and localization lengths.

Comments on Electron and Hole Transport in the Band Tail States of Amorphous Silicon at Low Temperatures

1989 ◽  
Vol 149 ◽  
Author(s):  
M. Silver ◽  
W. E. Spear
Keyword(s):  
Amorphous Silicon ◽  
Drift Mobility ◽  
Hole Transport ◽  
Experimental Results ◽  
Exponential Tail ◽  
Band Tail ◽  
State Distribution ◽  
Temperature Drift ◽  
Model Calculations ◽  
Tail State

ABSTRACTRecent experimental results on the low temperature drift mobility in amorphous silicon are examined on the basis of the approach to hopping transport developed by Silver and Bässler. It is shown on general grounds that the main features of the experimental results cannot be explained by a purely exponential tail state distribution, but are consistent with the distribution used by Spear and Cloude (1988) in model calculations.

scholarly journals Electrothermal transport induced material reconfiguration and performance degradation of CVD-grown monolayer MoS2 transistors

2020 ◽  
Vol 4 (1) ◽  
Author(s):  
Ansh ◽  
Jeevesh Kumar ◽  
Gaurav Sheoran ◽  
Mayank Shrivastava
Keyword(s):  
Low Temperature ◽  
High Field ◽  
Impact Ionization ◽  
Operating Regime ◽  
Kelvin Probe ◽  
Current Decay ◽  
Electrical Stress ◽  
Field Operation ◽  
Gate Control ◽  
And Performance

Abstract Device and material reliability of 2-dimensional materials, especially CVD-grown MoS2, has remained un-addressed since 2011 when the first TMDC transistor was reported. For its potential application in next generation electronics, it is imperative to update our understanding of mechanisms through which MoS2 transistors’ performance degrades under long-term electrical stress. We report, for CVD-grown monolayer MoS2, results on temporal degradation of material and device performance under electrical stress. Both low and high field regimes of operation are explored at different temperatures, gate bias and stress cycles. During low field operation, current is found to saturate after hundreds of seconds of operation with the current decay time constant being a function of temperature and stress cycle. High field operation, especially at low temperature, leads to impact ionization assisted material and device degradation. It is found that high field operation at low temperature results in amorphization of the channel and is verified by device and kelvin probe force microscopy (KPFM) analyses. In general, a prolonged room temperature operation of CVD-grown MoS2 transistors lead to degraded gate control, higher OFF state current and negative shift in threshold voltage (VT). This is further verified, through micro-Raman and photoluminescence spectroscopy, which suggest that a steady state DC electrical stress leads to the formation of localized low resistance regions in the channel and a subsequent loss of transistor characteristics. Our findings unveil unique mechanism by which CVD MoS2 undergoes material degradation under electrical stress and subsequent breakdown of transistor behavior. Such an understanding of material and device reliability helps in determining the safe operating regime from device as well as circuit perspective.

Electron Transport and Conduction-Band-Tail States in a-Si:H Deposited with a Remote Hydrogen Plasma

1993 ◽  
Vol 297 ◽  
Author(s):  
C.E. Nebel ◽  
R.A. Street ◽  
N.M. Johnson ◽  
J. Walker
Keyword(s):  
Electron Transport ◽  
Conduction Band ◽  
Defect Density ◽  
Plasma Deposition ◽  
Hydrogen Plasma ◽  
Band Tail ◽  
Mobility Edge ◽  
Characteristic Energy ◽  
Tail State ◽  
Electron Transport Properties

Electron transport properties of a-Si:H prepared in a remote hydrogen plasma deposition reactor (RHPD) at TD = 400°C were investigated in the temperature regime 110 K ≤ T ≤ 300 K by time-of-flight and post-transit spectroscopy experiments. Based on these data the conduction-band-tail state distribution was calculated. In the energy range 85 meV ≤ Ec- E ≤ 350 meV below the mobility edge Ec the tail is well described by an exponential distribution with a characteristic energy of ≃ 21 meV. Deeper in the mobility gap (Ec-E > 350 meV) the tail smoothly passes over into the defect density which is approximately six orders of magnitude smaller than at the mobility edge. Comparisons with data deduced on conventionally prepared a-Si:H (RF-, DC-glow discharge) at TD = 230 °C show that electron transport and the conduction band tail of the RHPD material are comparable.

Dependence of Precursors on Solution-Processed SnO2 as Electron Transport Layers for CsPbBr3 Perovskite Solar Cells

NANO ◽  
2020 ◽  
Vol 15 (12) ◽  
pp. 2050161
Author(s):  
Zhuang Liu ◽  
Jianlin Chen ◽  
Caiyou Huang ◽  
Too Gideon Kiprono ◽  
Wusong Zhao ◽  
...  
Keyword(s):  
Solar Cells ◽  
Electron Transport ◽  
Low Temperature ◽  
Short Circuit ◽  
Perovskite Solar Cells ◽  
Hole Transport ◽  
Transport Layer ◽  
Solution Processed ◽  
Flexible Polymer ◽  
Temperature Solution

In this paper, three kinds of SnO2 precursors were comparatively investigated for low temperature solution-processed SnO2 films as electron transport layers (ETL) of CsPbBr3 perovskite solar cells (PSCs). It was found that the precursor state and solvent type played an important role on the crystallinity and film-forming performance of SnO2. All-inorganic hole-transport-layer-free planar CsPbBr3 PSCs with an architecture of FTO/SnO2/CsPbBr3/carbon were fabricated. The best-performing device with SnO2 as ETL by reflux condensation sol spin-coating technique delivered a champion power conversion efficiency (PCE) as high as 6.27%, with a short-circuit current density of 7.36[Formula: see text]mA[Formula: see text]cm[Formula: see text], an open-circuit voltage of 1.29[Formula: see text]V, and a fill factor of 65.9%. It was comparable to the highest PCE record 6.7% of the device with the same structure based on TiO2-ETL so far. Moreover, the CsPbBr3 devices without encapsulation exhibited good stability after being stored under ambient conditions with a relative humidity of [Formula: see text]% at room temperature over 1000[Formula: see text]h and 60[Formula: see text]C for 720[Formula: see text]h, respectively. The results promise the commercial potential of CsPbBr3 PSCs using reflux condensation low-temperature solution-processed SnO2 as ETLs for flexible polymer photovoltaic applications.

scholarly journals Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Optical Measurements ◽  
Electrical Performance ◽  
Large Area ◽  
Nanowire Network ◽  
P Type ◽  
Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

scholarly journals Low-temperature-processed metal oxide electron transport layers for efficient planar perovskite solar cells

Rare Metals ◽  
2021 ◽  
Author(s):  
Jia-Xing Song ◽  
Xin-Xing Yin ◽  
Zai-Fang Li ◽  
Yao-Wen Li
Keyword(s):  
Solar Cells ◽  
Electron Transport ◽  
Low Temperature ◽  
Metal Oxide ◽  
Low Cost ◽  
Perovskite Solar Cells ◽  
Transport Layer ◽  
Electron Transport Layer ◽  
Future Research ◽  
Low Temperature Preparation

Abstract As a promising photovoltaic technology, perovskite solar cells (pero-SCs) have developed rapidly over the past few years and the highest power conversion efficiency is beyond 25%. Nowadays, the planar structure is universally popular in pero-SCs due to the simple processing technology and low-temperature preparation. Electron transport layer (ETL) is verified to play a vital role in the device performance of planar pero-SCs. Particularly, the metal oxide (MO) ETL with low-cost, superb versatility, and excellent optoelectronic properties has been widely studied. This review mainly focuses on recent developments in the use of low-temperature-processed MO ETLs for planar pero-SCs. The optical and electronic properties of widely used MO materials of TiO2, ZnO, and SnO2, as well as the optimizations of these MO ETLs are briefly introduced. The commonly used methods for depositing MO ETLs are also discussed. Then, the applications of different MO ETLs on pero-SCs are reviewed. Finally, the challenge and future research of MO-based ETLs toward practical application of efficient planar pero-SCs are proposed. Graphical abstract

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