The Impact of the Extrinsic Device on HFET Performance

1991 ◽  
Vol 240 ◽  
Author(s):  
David R. Greenberg ◽  
Jesús A. Del Alamo
Keyword(s):  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Insulator ◽  
Figures Of Merit ◽  
Velocity Saturation ◽  
Heterostructure Field Effect Transistors ◽  
Source Resistance ◽  
Carrier Velocity ◽  
The Impact ◽  
Ultimate Limit

ABSTRACTThe extrinsic device is known to degrade the performance of heterostructure field-effect transistors (HFET's) through the introduction of a parasitic source resistance (Rs). To date, however, there has been no recognition of the fact that carrier velocity saturation (vsat) can occur in both the extrinsic source and drain, setting the ultimate limit on maximum drain current (I,D,max) and on the useful VGS swing in HFET's. In this study, we demonstrate the mechanisms through which vsat in the extrinsic device limits device performance, using AlGaAs/n+-InGaAs Metal-Insulator-Doped-channel FET's (MIDFET's) as a vehicle. These devices show that gm falls at a lower VGSthan does fT, by as much as 1 V. This reveals that there are two mechanisms at work. The approach of vsat in the extrinsic source first causes the small-signal source resistance (Ts)to rise rapidly, leading gm to decline but leaving fT unaffected. As the carrier velocity in the extrinsic device approaches Vsat more closely, there is an actual decline of the carrier velocity in the intrinsic device. This process degrades velocity-related figures of merit such as and fT.

AlGaN/GaN Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors (MOSHFETs) with the Delta-Doped Barrier Layer

2002 ◽  
Vol 743 ◽  
Author(s):  
Z. Y. Fan ◽  
J. Li ◽  
J. Y. Lin ◽  
H. X. Jiang ◽  
Y. Liu ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Cutoff Frequency ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Heterostructure ◽  
Heterostructure Field Effect Transistors ◽  
Gate Control

ABSTRACTThe fabrication and characterization of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with the δ-doped barrier are reported. The incorporation of the SiO2 insulated-gate and the δ-doped barrier into HFET structures reduces the gate leakage and improves the 2D channel carrier mobility. The device has a high drain-current-driving and gate-control capabilities as well as a very high gate-drain breakdown voltage of 200 V, a cutoff frequency of 15 GHz and a maximum frequency of oscillation of 34 GHz for a gate length of 1 μm. These characteristics indicate a great potential of this structure for high-power-microwave applications.

scholarly journals Does carrier velocity saturation help to enhance fmax in graphene field-effect transistors?

2020 ◽  
Vol 2 (9) ◽  
pp. 4179-4186 ◽  
Author(s):  
Pedro C. Feijoo ◽  
Francisco Pasadas ◽  
Marlene Bonmann ◽  
Muhammad Asad ◽  
Xinxin Yang ◽  
...  
Keyword(s):  
High Frequency ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drift Diffusion Model ◽  
Drift Diffusion ◽  
Velocity Saturation ◽  
Self Heating ◽  
Heating Effects ◽  
Carrier Velocity ◽  
High Frequency Performance

A drift–diffusion model including self-heating effects in graphene transistors to investigate carrier velocity saturation for optimal high frequency performance.

Gate Current Modeling for Insulating Gate III-N Heterostructure Field-Effect Transistors

2002 ◽  
Vol 743 ◽  
Author(s):  
Frederick W. Clarke ◽  
Fat Duen Ho ◽  
M. Asif Khan ◽  
Grigory Simin ◽  
J. Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Elevated Temperatures ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Wide Band ◽  
Gate Leakage ◽  
Gate Current ◽  
Heterostructure Field Effect Transistors ◽  
Voltage Swing

AbstractGate current plays an important role in determining the characteristics and limiting performance of GaN-based field effect transistors. In GaN-based HFETs, the gate current limits the gate voltage swing and, hence, the maximum device current. Since the electron transport across the wide band gap barrier layer involves trapping, under certain bias conditions, the gate current leads to the threshold voltage shifts and causes reliability problems. Under reverse bias, the gate leakage in GaN-based HFET dominates the minimum (pinch-off) drain current. Insulating gate HFETs (i.e. Metal Oxide Heterostructure Field Effect Transistors – MOSHFETs) have the gate leakage currents 4 – 6 orders of magnitude lower than HFETs, even at elevated temperatures up to 300 °C. In this paper, we report on the gate current characteristics in these devices at room and elevated temperatures. We propose a semi-empirical model for the current-voltage characteristics in these devices, which is in good agreement with experimental data. Our data also show that both tunneling and temperature activation are important factors in MOSHFETs. These results are important for possible applications of GaN MOSHFETs in high power amplifiers and power switches as well as in non-volatile memory devices and integrated circuits that will operate in a much wider temperature range than conventional silicon and GaAs devices.

RECENT PROGRESS ON GaN-BASED ELECTRON DEVICES

2006 ◽  
Vol 16 (02) ◽  
pp. 469-477
Author(s):  
Yasuhiro Uemoto ◽  
Yutaka Hirose ◽  
Tomohiro Murata ◽  
Hidetoshi Ishida ◽  
Masahiro Hikita ◽  
...  
Keyword(s):  
Noise Figure ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Low Noise ◽  
60 Ghz ◽  
Si Doping ◽  
Power Handling Capability ◽  
Source Resistance ◽  
State Breakdown ◽  
A Current

We present results of some novel AlGaN/GaN heterojunction field-effect transistors (HFETs) specifically developed for RF front-end and power applications. To reduce the parasitic resistance, two unique techniques: selective Si doping into contact area and a superlattice (SL) cap structure, are developed. With the selective Si doping method, a transistor with an on-state resistance as low as 1.86 Ω·mm and a Tx/Rx switch IC with very low insertion loss (0.26 dB) and very high power handling capability (P1dB over 40 dBm) were obtained. With the SL cap HFETs, an ultra low source resistance of 0.4 Ω·mm was achieved and excellent DC and RF performances were demonstrated. The typical characteristics of these HFETs are: maximum transconductance of over 400 mS/mm, maximum drain current of 1.2 A/mm, cut-off frequency of 60 GHz, maximum oscillation frequency of 140 GHz, and a very low noise figure of 0.7 dB with 15 dB gain at 12 GHz. For power applications, in order to significantly reduce fabrication cost, we fabricated the AlGaN/GaN HFET on a conductive Si substrate with a source-via grounding (SVG) structure. The device has a very low on-state sheet resistance of 1.9 mΩ·cm2, a high off-state breakdown voltage of 350 V, and a current handling capability of 150 A. In addition, a sub-nano second switching response with t r of 98 ps and t f of 96 ps with a current density as high as 2.0 kA/cm2 is demonstrated for the first time.

scholarly journals Nonlinearity Analysis of Quantum Capacitance and its Effect on Nano-Graphene Field Effect Transistor characteristics

2021 ◽  
Author(s):  
MUNINDRA MUNINDRA ◽  
DEVA NAND
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Charge Carrier Concentration ◽  
Single Layer Graphene ◽  
Quantum Capacitance ◽  
Large Area ◽  
Source Voltage ◽  
Current Calculation ◽  
The Impact

Abstract A simple, compact, and fundamental physics-based quasi-analytic model for Single layer graphene field effect transistors (GFETs) with large area graphene is presented in which the quantum mechanical density gradient method is utilised. The basic device physics of the two-dimensional (2D) graphene channel is studied analytically. This modeling leads to the precise drain current calculation of the GFETs. The drain current calculation for GFETs starts from charge carrier concentration, its density of states and quantum capacitance(QC). QC depends on the channel voltage as a function of gate to source voltage Vgs and drain to source voltage Vds primarily. The formulation of the drain current with velocity saturation has been done by the Monte Carlo simulation method. The performance of the analytical GFETs model is present the precise values of QC, its impact on drain current and transfer as well as output characteristics. The impact of QC at nanometer technology adds the nonlinearity to characteristics curves. The proposed method provides better results as compared with the previous analytical and simulated results.

scholarly journals Output Conductance of Line-TFETs for Different Device Parameters and its Effect on Basic Analog Circuits

2020 ◽  
Vol 15 (1) ◽  
pp. 1-7 ◽  
Author(s):  
Walter Gonçalez Filho ◽  
João Antonio Martino ◽  
Paula Ghedini Der Agopian
Keyword(s):  
Analog Circuits ◽  
Analog Circuit ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Common Source ◽  
Gate Length ◽  
Current Mirrors ◽  
Conduction Mechanisms ◽  
The Impact ◽  
Output Conductance

This work addresses the impact of different device parameters on the analog characteristics of Line-Tunneling Field Effect Transistors (Line-TFETs). Source-to-drain separation, pocket thickness, pocket doping, gate-source alignment and the gate length are varied in order to evaluate their impact on the conduction mechanisms and on the overall transfer characteristics of the device. The variation of the main parameters responsible for device variability (pocket thickness and doping and gate-source alignment) is performed in order to analyze their impact on current mirrors, revealing that gate-source overlap improves the analog characteristics of the Line-TFET and that pocket doping should be limited to values smaller than 1018cm-3. Even though the drain current and the transconductance (gm) of this device are proportional to the gate area, simulations compared to experimental data show that the output conductance (gd) of Line-TFETs is practically independent of the gate length. The conduction mechanisms were analyzed through numerical simulations, revealing that this unique characteristic is due to source-to-drain tunneling, which defines the average value of gd on the saturation-like region and does not depend upon the gate length. The impact of this characteristic on analog circuit design is illustrated considering the example of a common-source stage and comparing its design when using MOSFET devices. This example reveals that the designer may choose whether to increase gm or gd in order to increase the circuit gain when using Line-TFETs, fundamentally differing from the MOSFET design.  

Effects of Area Ratio on the Characteristics of Metal-Ferroelectric-Metal-Insulator-Semiconductor Field-Effect-Transistors (MFMIS FETs)

2019 ◽  
Vol 201 (1) ◽  
pp. 183-191
Author(s):  
Jing Sun ◽  
Yanping Li ◽  
Lei Cao ◽  
Jiaoyun Liu ◽  
Xiaorong Shi ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Drain Current ◽  
Area Ratio ◽  
Drain Voltage ◽  
Double Integral ◽  
Metal Insulator ◽  
Polarization Voltage ◽  
Ferroelectric Layer ◽  
Capacitance Voltage ◽  
Current Drain

The switching physics of ferroelectric, series capacitance theory and Pao and Sah’s double integral are used for describing the polarization-voltage (P-V) characteristic of ferroelectric layer, capacitance-voltage (C-V) characteristic of MFMIS capacitor, and drain current-gate voltage (ID-VGS) and drain current-drain voltage (ID-VDS) characteristics of MFMIS FET. The effects of the area ratio on the P-V, C-V, ID-VGS, and ID-VDS characteristics are discussed. The results indicate that with the increase of the area ratio, the P-V characteristic, memory windows of C-V and ID-VGS characteristics become saturated, while the drain current ON/OFF ratio and applied voltage for saturated memory window decrease.

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