Single-Wafer RTCVD of Polysilicon: a Complementary Step in Front-End Integrated Processing

1991 ◽  
Vol 224 ◽  
Author(s):  
Ahbmad Kermani
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Active Material ◽  
Controlled Environment ◽  
Solid Diffusion ◽  
Front End ◽  
Integrated Processing ◽  
Mos Gate ◽  
Elevated Source ◽  
Processing Steps

AbstractPolycrystalline silicon is used in the fabrication of integrated circuits in various applications. These include a MOS gate material, bipolar emitter and base contacts, trench refill, complementary material for elevated source / drain structures, solid diffusion source for formation of shallow junctions and the active material in thin film transistors. The deposition of polysilicon as the MOS gate electrode or the bipolar emitter contact follows the most critical processing steps in fabrication of these devices. Maximum reproducibility and highest device performance are achieved when the interfaces between the polysilicon and the underneath substrate are well controlled. This level of control can be obtained by combining the compatible processing steps under a controlled environment. Single-wafer RTCVD of polysilicon was introduced to complement the emerging front-end integrated processing technology for MOS, bipolar and BICMOS devices.

Polysilicon Integration

1990 ◽  
Vol 182 ◽  
Author(s):  
J. Ellul ◽  
I.D. Calder
Keyword(s):  
Integrated Circuits ◽  
Active Material ◽  
Three Dimensional ◽  
Cumulative Effect ◽  
Bicmos Technology ◽  
Silicon Integrated Circuits ◽  
New Process ◽  
Improved Performance ◽  
Polysilicon Emitters ◽  
Mos Gate

AbstractPolycrystalline silicon has found numerous applications in silicon integrated circuits, initially as a MOS gate material, and later for advanced isolation, capacitor electrodes, resistors, interconnect, bipolar emitters and bases, trench refill, doping sources, and the active material in thin film transistors. Integration of these techniques in a BiCMOS technology requires knowledge of the interactions between the processing steps, and their cumulative effect on the final device and circuit operation. New process techniques also present opportunities for process simplification, added functionality, or improved performance. Examples of polysilicon applications that interact with other process steps and influence device performance are P+ and N+ poly gates and silicidation of gate poly. Silicidation improves circuit speed and provides additional integration opportunities in the form of faster local interconnect, but it may create a problem for older designs with synchronous timing circuitry. More innovative integration of polysilicon includes improved deposition techniques, such as the use of amorphous silicon, “Lo-Hi” poly, in sinat doping, and deposition from disilane sources enable more flexible process design. Other innovations include polysilicon emitters, bases, and buried sinkers in bipolar design, polysilicon sidewall spacers in CMOS, and polysilicon based active transistors for display applications and three dimensional integration.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Ultra-Shallow junctions in silicon using amorphous and polycrystalline silicon solid diffusion sources

1991 ◽  
Vol 20 (3) ◽  
pp. 261-265 ◽  
Author(s):  
Keunhyung Park ◽  
Shubneesh Batra ◽  
Sanjay Banerjee ◽  
Gayle Lux
Keyword(s):  
Polycrystalline Silicon ◽  
Solid Diffusion ◽  
Shallow Junctions ◽  
Ultra Shallow Junctions

Ultra-low Residue Flux Applications in RF Front-End Packages

2020 ◽  
Vol 2020 (1) ◽  
pp. 000125-000130
Author(s):  
Leo Hu ◽  
Sze Pei Lim
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Reflow Process ◽  
Reliability Study ◽  
Rf Switches ◽  
Front End ◽  
Rf Front End ◽  
Package Reliability

Abstract With the leap into the 5G era, the demand for improvements in the performance of mobile phones is on the rise. This is also true for the quantity of radio frequency (RF) front-end integrated circuits (ICs), especially for RF switches and low noise amplifiers (LNA). It is well-known that improvements in performance depend on the combination of new design, package technology, and choice of materials. Ultra-low residue (ULR) flux is an innovative, truly no-clean, flip-chip bonding material. By using ULR flux, the typical water-wash cleaning process can be removed and, in some instances, package reliability can be improved as well. This simplified assembly process will help to reduce total packaging costs. This paper will discuss the application of ULR fluxes on land grid arrays (LGAs) and quad-flat no-leads/dual-flat no-leads (QFN/DFN) packages for RF front-end ICs, as well as the reflow process. The solder joint strength and reliability study will be shared as well.

Integration of a K-Band Receiver Front-End Using a Copper Core Printed Circuit Board

2018 ◽  
Vol 2018 (1) ◽  
pp. 000384-000388
Author(s):  
Brian Curran ◽  
Jacob Reyes ◽  
Christian Tschoban ◽  
Ivan Ndip ◽  
Klaus-Dieter Lang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Antenna Arrays ◽  
High Frequency ◽  
Printed Circuit Board ◽  
Cost Effective ◽  
Circuit Board ◽  
Front End ◽  
High Bandwidth ◽  
Increasing Demand ◽  
K Band

Abstract Increasing demand for high bandwidth wireless satellite connections and telecommunications has resulted in interest in steerable antenna arrays in the GHz frequency range. These applications require cost-effective integration technologies for high frequency and high power integrated circuits (ICs) using GaAs, for example. In this paper, an integration platform is proposed, that enables GaAs ICs to be directly placed on a copper core inside cavities of a high frequency laminate for optimal cooling purposes. The platform is used to integrate a K-Band receiver front-end, composed of four GaAs ICs, with linear IF output power for input powers above −40dBm and a temperature of 42°C during operation.

Planarization of Deep Structures Using Self-Leveling Materials

2012 ◽  
Vol 2012 (1) ◽  
pp. 000079-000083
Author(s):  
Dongshun Bai ◽  
Michelle Fowler ◽  
Curtis Planje ◽  
Xie Shao
Keyword(s):  
Integrated Circuits ◽  
Microelectromechanical Systems ◽  
Flat Panel Displays ◽  
New Materials ◽  
Flat Panel ◽  
Light Emitting ◽  
Good Thermal Stability ◽  
Device Integration ◽  
Potential Applications ◽  
Processing Steps

To achieve device integration that will allow the manufacture of smaller, more functional, and more efficient microelectronics, the industry increasingly requires materials to fill and planarize devices with deep structures. Brewer Science has developed several new self-leveling materials to address these planarization needs. These newly developed materials are designed to be either temporary materials that can be removed after their use in processing steps or permanent materials that can stay in a device for its lifetime. These new materials can be applied easily by means of a spin-coating process. They are unique because they can fill and planarize high-aspect-ratio trenches and vias hundreds of microns deep. Some of the materials are photosensitive and can be patterned using photolithography. All of the photosensitive materials in this paper can be developed with industry-accepted solvents and some with an aqueous TMAH solution. Because of their good thermal stability, high transparency, and excellent planarization properties, these materials have potential applications for microelectromechanical systems (MEMS), 3-D integrated circuits, light-emitting diodes (LEDs), semiconductors, flat-panel displays, and related microelectronic and optoelectronic devices. This paper will discuss the properties of these new materials and will present the filling and leveling results obtained in several applications.

Variation of Local Mechanical Stress During the Different Processing Steps of Ic-Isolation: a Micro-Raman Spectroscopy Study

1993 ◽  
Vol 308 ◽  
Author(s):  
Ingrid De Wolf ◽  
Herman E. Maes ◽  
Hans Norström
Keyword(s):  
Raman Spectroscopy ◽  
Integrated Circuits ◽  
Mechanical Stress ◽  
Local Variation ◽  
Micro Raman Spectroscopy ◽  
Induced Stress ◽  
Last Stage ◽  
Edge Force ◽  
Field Oxide ◽  
Processing Steps

ABSTRACTLocal mechanical stress introduced in the silicon substrate during the successive steps of poly-buffered local isolation of MOS integrated circuits is studied with micro-Raman spectroscopy. It is shown that the magnitude and the local variation of the stress is highly affected by the different processing steps. After deposition of the nitride mask, the stress can be described as caused by an edge-force. Field oxidation reduces the mask-induced stress but introduces thermal stress from the field oxide. Also the formation of the bird's beak gives rise to additional local tensile stress, especially at the tip of the bird's beak. Removal of the nitride mask results in a partial relaxation: the stress caused by the bird's beak relaxes. In this last stage of the isolation process, the stress image is mostly determined by the field oxide.

scholarly journals Using Open-Source Components to Process Interferometric TerraSAR-X Spotlight Data

2013 ◽  
Vol 2013 ◽  
pp. 1-13 ◽  
Author(s):  
Michael Jendryke ◽  
Timo Balz ◽  
Houjun Jiang ◽  
Mingsheng Liao ◽  
Uwe Stilla
Keyword(s):  
Satellite Images ◽  
High Spatial Resolution ◽  
Las Vegas ◽  
Beam Steering ◽  
Object Oriented ◽  
Research Community ◽  
The Usa ◽  
Integrated Processing ◽  
Shift Frequency ◽  
Processing Steps

We address the processing of interferometric TerraSAR-X and TanDEM-X spotlight data. Processing steps necessary to derive interferograms at high spatial resolution from bi- and monostatic satellite images will be explained. The spotlight image mode is a beam steering technique focusing the antenna on a specific ground area. This results in a linear Doppler shift frequency in azimuth direction, which has to be matched to the master image. While shifting the interpolation kernel in azimuth during resampling, the frequency spectrum of the slave image is aligned to the master image. We show how to process bistatic TanDEM-X images and propose an integrated processing option for monostatic TerraSAR-X data in the Delft Object-oriented Radar Interferometric Software (DORIS). The paper focuses on the implementation of this algorithm for high-resolution spotlight InSAR in a public domain tool; hence, it becomes available to a larger research community. The results are presented for three test areas: Uluru in Australia, Las Vegas in the USA, and Lüneburg in Germany.

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