Polysilicon Integration

1990 ◽  
Vol 182 ◽  
Author(s):  
J. Ellul ◽  
I.D. Calder
Keyword(s):  
Integrated Circuits ◽  
Active Material ◽  
Three Dimensional ◽  
Cumulative Effect ◽  
Bicmos Technology ◽  
Silicon Integrated Circuits ◽  
New Process ◽  
Improved Performance ◽  
Polysilicon Emitters ◽  
Mos Gate

AbstractPolycrystalline silicon has found numerous applications in silicon integrated circuits, initially as a MOS gate material, and later for advanced isolation, capacitor electrodes, resistors, interconnect, bipolar emitters and bases, trench refill, doping sources, and the active material in thin film transistors. Integration of these techniques in a BiCMOS technology requires knowledge of the interactions between the processing steps, and their cumulative effect on the final device and circuit operation. New process techniques also present opportunities for process simplification, added functionality, or improved performance. Examples of polysilicon applications that interact with other process steps and influence device performance are P+ and N+ poly gates and silicidation of gate poly. Silicidation improves circuit speed and provides additional integration opportunities in the form of faster local interconnect, but it may create a problem for older designs with synchronous timing circuitry. More innovative integration of polysilicon includes improved deposition techniques, such as the use of amorphous silicon, “Lo-Hi” poly, in sinat doping, and deposition from disilane sources enable more flexible process design. Other innovations include polysilicon emitters, bases, and buried sinkers in bipolar design, polysilicon sidewall spacers in CMOS, and polysilicon based active transistors for display applications and three dimensional integration.

Single-Wafer RTCVD of Polysilicon: a Complementary Step in Front-End Integrated Processing

1991 ◽  
Vol 224 ◽  
Author(s):  
Ahbmad Kermani
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Active Material ◽  
Controlled Environment ◽  
Solid Diffusion ◽  
Front End ◽  
Integrated Processing ◽  
Mos Gate ◽  
Elevated Source ◽  
Processing Steps

AbstractPolycrystalline silicon is used in the fabrication of integrated circuits in various applications. These include a MOS gate material, bipolar emitter and base contacts, trench refill, complementary material for elevated source / drain structures, solid diffusion source for formation of shallow junctions and the active material in thin film transistors. The deposition of polysilicon as the MOS gate electrode or the bipolar emitter contact follows the most critical processing steps in fabrication of these devices. Maximum reproducibility and highest device performance are achieved when the interfaces between the polysilicon and the underneath substrate are well controlled. This level of control can be obtained by combining the compatible processing steps under a controlled environment. Single-wafer RTCVD of polysilicon was introduced to complement the emerging front-end integrated processing technology for MOS, bipolar and BICMOS devices.

3-D Integration Technology for High Performance Detector Arrays

2006 ◽  
Vol 970 ◽  
Author(s):  
Dorota Temple ◽  
Christopher A. Bower ◽  
Dean Malta ◽  
James E. Robinson ◽  
Phillip R. Coffman ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Focal Plane ◽  
High Performance ◽  
Three Dimensional ◽  
Focal Plane Arrays ◽  
Detector Arrays ◽  
Silicon Integrated Circuits ◽  
Military Systems ◽  
On Chip ◽  
Chip Signal

ABSTRACTThis paper describes a technology for three-dimensional (3-D) integration of multiple layers of silicon integrated circuits. The technology promises to dramatically enhance on-chip signal processing capabilities of a variety of detector devices hybridized with Si electronics. The focus of the paper is on high performance infrared focal plane arrays based on HgCdTe, which offer the ultimate in infrared sensitivity and find application in high performance military systems. Performance data from test FPA devices with integrated multilayer Si stacks are discussed in this paper.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Electrical Invasiveness of Grinding and Polishing Silicon Integrated Circuits Down to 1 μm Remaining Silicon Thickness

2016 ◽  
Author(s):  
Robert Chivas ◽  
Scott Silverman ◽  
Michael DiBattista ◽  
Ulrike Kindereit
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Electron Hole ◽  
Analysis Techniques ◽  
Silicon Integrated Circuits ◽  
Electron Hole Pair ◽  
Pair Generation ◽  
Silicon Thickness ◽  
Performance Timing ◽  
Grinding And Polishing

Abstract Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (< 5 um global, ~ 1 um local) remaining thickness is presented.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

scholarly journals Fabrication of Eutectic Ga-In Nanowire Arrays Based on Plateau–Rayleigh Instability

Molecules ◽  
2021 ◽  
Vol 26 (15) ◽  
pp. 4616
Author(s):  
Takashi Ikuno ◽  
Zen Somei
Keyword(s):  
Integrated Circuits ◽  
Substrate Surface ◽  
Three Dimensional ◽  
Average Diameter ◽  
Nanowire Arrays ◽  
Scanning Probe ◽  
Rayleigh Instability ◽  
Simple Method ◽  
Flat Substrate ◽  
Metal Nanowire

We have developed a simple method of fabricating liquid metal nanowire (NW) arrays of eutectic GaIn (EGaIn). When an EGaIn droplet anchored on a flat substrate is pulled perpendicular to the substrate surface at room temperature, an hourglass shaped EGaIn is formed. At the neck of the shape, based on the Plateau–Rayleigh instability, the EGaIn bridge with periodically varying thicknesses is formed. Finally, the bridge is broken down by additional pulling. Then, EGaIn NW is formed at the surface of the breakpoint. In addition, EGaIn NW arrays are found to be fabricated by pulling multiple EGaIn droplets on a substrate simultaneously. The average diameter of the obtained NW was approximately 0.6 μm and the length of the NW depended on the amount of droplet anchored on the substrate. The EGaIn NWs fabricated in this study may be used for three-dimensional wiring for integrated circuits, the tips of scanning probe microscopes, and field electron emission arrays.

scholarly journals High-Performance On-Chip Silicon Beamsplitter Based on Subwavelength Metamaterials for Enhanced Fabrication Tolerance

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1304
Author(s):  
Raquel Fernández de Cabo ◽  
David González-Andrade ◽  
Pavel Cheben ◽  
Aitor V. Velasco
Keyword(s):  
Integrated Circuits ◽  
Fundamental Mode ◽  
High Performance ◽  
Three Dimensional ◽  
High Sensitivity ◽  
Power Splitting ◽  
Excess Loss ◽  
Power Splitters ◽  
On Chip ◽  
Efficient Power

Efficient power splitting is a fundamental functionality in silicon photonic integrated circuits, but state-of-the-art power-division architectures are hampered by limited operational bandwidth, high sensitivity to fabrication errors or large footprints. In particular, traditional Y-junction power splitters suffer from fundamental mode losses due to limited fabrication resolution near the junction tip. In order to circumvent this limitation, we propose a new type of high-performance Y-junction power splitter that incorporates subwavelength metamaterials. Full three-dimensional simulations show a fundamental mode excess loss below 0.1 dB in an ultra-broad bandwidth of 300 nm (1400–1700 nm) when optimized for a fabrication resolution of 50 nm, and under 0.3 dB in a 350 nm extended bandwidth (1350–1700 nm) for a 100 nm resolution. Moreover, analysis of fabrication tolerances shows robust operation for the fundamental mode to etching errors up to ± 20 nm. A proof-of-concept device provides an initial validation of its operation principle, showing experimental excess losses lower than 0.2 dB in a 195 nm bandwidth for the best-case resolution scenario (i.e., 50 nm).

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