Surface Mount Technology (SMT) Substrate Material Requirements - A Brief Review

1987 ◽  
Vol 108 ◽  
Author(s):  
A. Mahammad Ibrahim

ABSTRACTThe state of the art for the printed circuit (pc) industry is the Surface Mount Technology (SMT) using leadless ceramic chip carriers (LCCCs). The SMT technique is used to design, fabricate, and assemble affordable high-speed, high-density electronic modules with reduced size and weight. However, to take full advantage of the SMT, new high-performance printed circuit board (PCB) substrate materials must be developed, especially if the goal is to satisfy the high reliability required in military applications. The most critical requirement is matching the in-plane coefficient of thermal expansion (CTE) with the SMT-PCB's and the chip carriers (LCCCs) to reduce the solderjoint stresses during thermal cycling. Solder-joint reliability can be improved significantly by tailoring the in-plane CTE to approximately 6–7 ppm/°C (of the alumina chip carrier) using Kevlar and/or quartz fabric-reinforced polymer composites, instead of conventional glass composites. Less attention has been focussed on other important requirements, e.g., out-of-plane (Z-axis) expansion, glass transition temperature (Tg), dielectric constant, and resin microcracking, which also play important roles in the overall performance of the substrate materials. For example, high Z-expansion puts additional strain on the plated through holes (PTH), thereby affecting PTR reliability. A low Tg significantly increases the amount of thermal stress imposed during thermal cycling on solder joints and PTH, and leads to failures. This paper contains a brief review of the requirements of a SMT-PCB substrate material, including such critical parameters as: in-plane CTE, out-of-plane CTE, Tg, dielectric constant, fiber-to-resin ratio, and resin microcracking, and their effects on solder joint reliability, PTH reliability, dimensional stability, and electrical performance.

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000542-000553
Author(s):  
Betty H. Yeung ◽  
Torsten Hauck ◽  
Brett Wilkerson ◽  
Thomas Koschmieder

The solder joint reliability of semiconductor package interconnects is critical to product durability. A dominant failure mode is solder fatigue due to the CTE mismatch between BGA component and PCB at thermal cycling. It is well known that besides thermal expansion mismatch of component and board, the solder joint geometry has a great impact on fatigue behavior and time to failure. In this study, a combination of Surface Evolver and finite element analysis are use to predict the solder joint shapes for the assembly of medium pin count BGA's and to estimate the reliability at accelerated temperature cycling conditions. Results of Surface Evolver are compared with the assumption of a truncated sphere. The solder shape predictions are applied for a subsequent thermo-mechanical analysis of the BGA assembly. Inelastic creep deformation is evaluated for critical solder balls, and the Coffin-Manson relation is used to estimate the solder joint lifetime. The entire simulation procedure will be demonstrated for a product design study for high reliability automotive BGA's. A fractional factorial design is defined that considers solder sphere diameter and solder pad sizes on BGA substrate and on PCB side. Resulting creep values and lifetime estimates will be compared.


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