A High Performance Submicrometer CMOS/SOI Technology Using Ultrathin Silicon Films on Simox

1987 ◽  
Vol 107 ◽  
Author(s):  
P.K. Vasudev ◽  
K.W. Terrill ◽  
S. Seymour
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Silicon Films ◽  
Ring Oscillator ◽  
Cmos Integrated Circuits ◽  
And Performance ◽  
High Transconductance ◽  
Soi Technology ◽  
Very High

AbstractThe use of ultrathin SIMOX wafers for fabricating submicrometer CMOS integrated circuits is described. It is demonstrated from ring oscillator speeds that properly designed devices can exhibit very high transconductance and performance superior to circuits using bulk Si.

III-V HETEROJUNCTION BIPOLAR TRANSISTORS FOR HIGH-SPEED APPLICATIONS

1990 ◽  
Vol 01 (03n04) ◽  
pp. 245-301 ◽  
Author(s):  
M.F. CHANG ◽  
P.M. ASBECK
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
High Speed ◽  
High Performance ◽  
Growth Parameters ◽  
Bipolar Transistors ◽  
System Requirements ◽  
Potential Impact ◽  
Computational Systems ◽  
Very High

Recent advances in communication, radar and computational systems demand very high performance electronic circuits. Heterojunction bipolar transistors (HBTs) have the potential of providing a more efficient solution to many key system requirements through intrinsic device advantages than competing technologies. This paper reviews the present status of GaAs and InP-based HBT technologies and their applications to digital, analog, microwave and multifunction circuits. It begins with a brief review of HBT device concepts and critical epitaxial growth parameters. Issues important for device modeling and fabrication technologies are discussed. The paper then highlights the performance and the potential impact of HBT devices and integrated circuits in various application areas. Key prospects for future HBT development are also addressed.

Thermal Issues in Next Generation Integrated Circuits

2003 ◽  
Author(s):  
Siva Gurrum ◽  
Shivesh Suman ◽  
Yogendra Joshi ◽  
Andrei Fedorov
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Power Dissipation ◽  
High Performance ◽  
Electronic Devices ◽  
Heat Removal ◽  
Current Generation ◽  
Fundamental Limits ◽  
Convection Boundary ◽  
And Performance

Effective cooling of electronic chips is crucial for reliability and performance of electronic devices. Steadily increasing power dissipation in both devices and interconnects motivate the investigation of chip-centric thermal management as opposed to traditional package-centric solutions. In this work, we explore the fundamental limits for heat removal from a model chip for various configurations. Temperature rise when the chip is embedded in an infinite solid is computed for different thermal conductivities of the medium to pin down the best that can be achieved with conduction based thermal management. Next, a chip attached to a spreader plate with convection boundary condition on top was considered. A brief review of interface thermal resistances and partitioning of overall thermal resistance is presented for current generation microprocessors. Based upon the analysis it is concluded that far-term cooling solutions might necessitate integration with chip/interconnect-stack to meet the challenges. In addition, this would require concurrent thermal and electrical design/fabrication of future high-performance microprocessors.

scholarly journals Evaluation of Meshed Reference Planes for High Performance Applications

2000 ◽  
Vol 22 (3) ◽  
pp. 175-187 ◽  
Author(s):  
N. D. Codreanu ◽  
P. Svasta ◽  
V. Golumbeanu ◽  
L. Gál
Keyword(s):  
Integrated Circuits ◽  
High Frequency ◽  
High Speed ◽  
High Performance ◽  
Network Analyzer ◽  
High Frequencies ◽  
High Speeds ◽  
University Of Budapest ◽  
Very High Frequencies ◽  
Very High

The actual generations of integrated circuits are characterized, inter alia, by very high frequencies or very high speeds. The dramatic evolution ofthe semiconductor's technology establishes a greater “pressure” to the design and the manufacturing of the passive interconnection structure from PCB/MCM electronic modules. In these conditions the reference planes (power and ground planes) have a more and more important contribution. The paper intents to present the effect of different configuration reference planes on the characteristics of the high speed/high frequency interconnection lines. The first part deals with modeling and simulation of usual practical interconnection geometries. A computer modeling of meshed structures was realized and Spice models for a good compatibility with circuit simulators were obtained.S-,Y-,Z- parameters and radiation patterns were calculated, too. The second part contains measurements made by a vector network analyzer as regards to different practical configurations manufactured at Technical University of Budapest.

Preparation and Performance Research of Polyimide Modified Nylon Resin

2011 ◽  
Vol 236-238 ◽  
pp. 548-551
Author(s):  
Hong Kai Zhao ◽  
Li Guang Xiao ◽  
Xiao Jing Zhang
Keyword(s):  
Bisphenol A ◽  
High Performance ◽  
Water Resistance ◽  
Hot Spot ◽  
Microscopic Analysis ◽  
Infrared Analysis ◽  
Lamellar Crystals ◽  
And Performance ◽  
Performance Research ◽  
Very High

High performance trend of plastics has become a hot spot of current research. Select bisphenol A dianhydride and bisphenol A diamine with excellent water resistance as the reactant monomers to obtain anhydride-terminated polyimide with very high molecular weight by two-step polymerization, graft the active radicals of acyl caprolactam using the activity of anhydride and obtain PI modified nylon resin by polymerization. It is proved that the reaction in each above step is successful through infrared analysis. Through microscopic analysis, the molecules of polyimide does not enter crystallization phase of nylon resin, but forms compact lamellar crystals existing in nylon matrix.

Compliant Wafer Level Package

2001 ◽  
Author(s):  
Chirag Patel ◽  
Kevin P. Martin ◽  
James D. Meindl
Keyword(s):  
Performance Analysis ◽  
Integrated Circuits ◽  
High Performance ◽  
Wafer Level ◽  
Electronic Products ◽  
Packaging Technology ◽  
Technology Roadmap ◽  
Wafer Level Packaging ◽  
And Performance ◽  
Wafer Level Package

Abstract A high I/O density and high performance wafer level packaging technology called the Compliant Wafer Level Package (CWLP) is reported. The necessity for compliant interconnects in upcoming generations of electronic products is discussed by analyzing the technology requirements projected by the International Technology Roadmap for Semiconductors (ITRS). To be a true wafer level package, the technology should have following three characteristics11: I) package all Integrated Circuits (ICs) intact on wafer at once, II) perform wafer level test and burn-in, and III) assemble the WLP on the system board without using an underfill. Compliant interconnects are essential to accomplishing wafer level test and assembly without underfill. These topics are discussed in the paper followed by fabrication and performance analysis of the CWLP technology.

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