Effect of SiC Power DMOSFET Threshold-Voltage Instability

2008 ◽  
Vol 1069 ◽  
Author(s):  
Aivars Lelis ◽  
D. Habersat ◽  
R. Green ◽  
A. Ogunniyi ◽  
M. Gurfinkel ◽  
...  
Keyword(s):  
Leakage Current ◽  
Threshold Voltage ◽  
Power Loss ◽  
Gate Oxide ◽  
Primary Effect ◽  
Bias Stress ◽  
Voltage Instability ◽  
Oxide Traps ◽  
State Resistance

ABSTRACTWe have performed bias-stress induced threshold-voltage instability measurements on fully processed 4-H SiC power DMOSFETs as a function of bias-stress time, field, and temperature and have observed similar instabilities to those previously reported for lateral SiC MOSFET test structures. This effect is likely due to electrons tunneling into and out of near-interfacial oxide traps that extend spatially into the gate oxide. As long as the threshold voltage is set high enough to preclude the onset of subthreshold drain leakage current in the blocking state, then the primary effect of this instability is to increase the on-state resistance. For well-behaved power DMOSFETs, this would increase the power loss by no more than a few percent.

Bias Stress-Induced Threshold-Voltage Instability of SiC MOSFETs

2006 ◽  
Vol 527-529 ◽  
pp. 1317-1320 ◽  
Author(s):  
Aivars J. Lelis ◽  
Daniel B. Habersat ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Linear Increase ◽  
Oxide Semiconductor ◽  
Bias Stress ◽  
Voltage Instability ◽  
Current Voltage ◽  
Oxide Traps ◽  
Charge Tunneling

We have observed instability in the threshold voltage, VT, of SiC metal-oxide semiconductor field-effect transistors (MOSFETs) due to gate-bias stressing. This effect has routinely been observed by us in all 4H and 6H SiC MOSFETs from three different manufacturers—even at room temperature. A positive-bias stress, applying an electric field of about 1 to 2 MV/cm across the gate oxide, for 3 minutes followed by a negative-bias stress for another 3 minutes typically results in a shift of the ID-VGS current-voltage characteristic in the range of 0.25 to 0.5 V and is repeatable. We speculate that this effect is due to the presence of a large number of near-interfacial oxide traps that presumably lie in the oxide transition region that extends several nm into the oxide from the SiC interface, caused by the presence of C and strained SiO2. This instability is consistent with charge tunneling in and out of these near-interfacial oxide traps, which in irradiated Si MOSFETs has been attributed to border traps. Also consistent with charge tunneling is the observed linear increase in the magnitude of the SiC VT instability with log (time).

Review on Switches for Power Applications: Macro to Micro

2019 ◽  
Vol 12 (3) ◽  
pp. 200-209
Author(s):  
Femi Robert
Keyword(s):  
Leakage Current ◽  
Power Loss ◽  
Low Cost ◽  
Electrical System ◽  
High Isolation ◽  
Fast Switching ◽  
Environmental Friendly ◽  
State Resistance ◽  
Very High ◽  
Bulk Production

Background: Switches are important component in electrical system. The switches needs to have the advantages of low ON-state resistance, very high OFF-state resistance, high isolation, no leakage current, less power loss, fast switching, high linearity, small size, arcless and low cost in bulk production. Also these switches have to be reliable and environmental friendly. Methods: In this paper, macro and microswitches for power applications are extensively reviewed and summarized. Various types of switches such as mechanical, solid-state, hybrid and micromechanical switches have been used for power applications are reviewed. The importance and challenge in achieving arcless switching is presented. Results: The use of micromechanical switches for power applications, actuation techniques, switching modes, reliability and lifetime are also reviewed. The modeling and design challenges are also reviewed. Conclusion: The applications of micromechanical switches shows that the switches can reduce the leakage current in battery operated systems and reduce the size of the system considerably.

Research on Threshold Voltage Instability in SiC MOSFET Devices with Precision Measurement

2019 ◽  
Vol 954 ◽  
pp. 133-138
Author(s):  
Ao Liu ◽  
Song Bai ◽  
Run Hua Huang ◽  
Tong Tong Yang ◽  
Hao Liu
Keyword(s):  
Threshold Voltage ◽  
Precision Measurement ◽  
Gate Dielectric ◽  
Interface Traps ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Experimental Platform ◽  
Bias Stress ◽  
Voltage Instability ◽  
Voltage Drift

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

Threshold-Voltage Instability in SiC MOSFETs Due to Near-Interfacial Oxide Traps

2016 ◽  
Vol 858 ◽  
pp. 585-590 ◽  
Author(s):  
Aivars J. Lelis ◽  
Ronald Green ◽  
Daniel B. Habersat
Keyword(s):  
Threshold Voltage ◽  
Charge Trapping ◽  
Test Methods ◽  
Device Failure ◽  
Voltage Instability ◽  
Oxide Trap ◽  
Oxide Traps ◽  
Trap Activation

There are two basic mechanisms that affect the threshold-voltage (VT) stability: oxide-trap activation and oxide-trap charging. Once additional oxide traps are activated, then they are free to participate in the charge-trapping processes that can, especially for older vintage devices, result in large VT shifts and potential device failure. More recent commercially-available devices show much smaller effects, and minimal trap activation. Given the dramatic improvements, it is now imperative that improved test methods be employed to properly separate out bad devices from good devices.

Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements

2008 ◽  
Vol 55 (8) ◽  
pp. 1835-1840 ◽  
Author(s):  
Aivars J. Lelis ◽  
Daniel Habersat ◽  
Ronald Green ◽  
Aderinto Ogunniyi ◽  
Moshe Gurfinkel ◽  
...  
Keyword(s):  
Time Dependence ◽  
Threshold Voltage ◽  
Bias Stress ◽  
Voltage Instability

scholarly journals Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs at High Temperatures

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000275-000280 ◽  
Author(s):  
R. J. Kaplar ◽  
D. R. Hughart ◽  
S. Atcitty ◽  
J. D. Flicker ◽  
S. DasGupta ◽  
...  
Keyword(s):  
Leakage Current ◽  
Threshold Voltage ◽  
Gate Voltage ◽  
First Generation ◽  
Second Generation ◽  
Power Mosfets ◽  
Bias Stress ◽  
Bias Temperature Stress ◽  
Increasing Temperature ◽  
Negative Gate Voltage

Commercially available, 1200 V SiC power MOSFETs have been characterized under bias-temperature stress conditions. Two generations of devices from a single manufacturer were tested. For the first-generation MOSFETs, both plastic- and metal-packaged devices were evaluated, whereas for the second-generation MOSFETs, only plastic-packaged devices were tested. Threshold voltage was observed to decrease with increasing temperature in the absence of gate bias stress, as expected. Drain leakage current increased with increasing temperature above the rated temperature of 125°C for first-generation plastic-packaged parts, with the leakage ~10× higher for the plastic-packaged parts compared to the metal-packaged parts. A negative gate voltage was shown to reduce drain leakage current for the metal-packaged parts only, suggesting a parasitic leakage path associated with the plastic packaging. The threshold voltage shift ΔVT was minimal for T < 125°C. ΔVT increased with increasing temperature above 125°C, and was larger for negative gate voltage bias stress, suggesting that the oxide is more sensitive to trapping of holes than trapping of electrons. ΔVT was insensitive to the type of package. The second-generation SiC MOSFET showed significantly less susceptibility to bias temperature stress, especially for negative gate voltage, indicating improvement in device design and/or processing in the second-generation MOSFET. Switching gate stress showed complex behavior, with a rapid initial shift in VT followed by a much slower shift. Initial testing indicates a strong dependence on duty cycle and possible influence of self-heating. More detailed study of reliability under switching conditions is needed.

Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

2020 ◽  
Vol 1004 ◽  
pp. 554-558
Author(s):  
Kwangwon Lee ◽  
Young Ho Seo ◽  
Taeseop Lee ◽  
Kyeong Seok Park ◽  
Martin Domeij ◽  
...  
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Gate Bias ◽  
Annealed Condition ◽  
Threshold Voltage Shift ◽  
Bias Stress ◽  
Phosphorus Doped ◽  
Gate Bias Stress ◽  
Gate Oxide Integrity

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

Threshold Voltage Instability in 4H-SiC MOSFETs with Nitrided Gate Oxide Revealed by Non-relaxation Method

2015 ◽  
Author(s):  
M. Sometani ◽  
D. Okamoto ◽  
S. Harada ◽  
H. Ishimori ◽  
S. Takasu ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Relaxation Method ◽  
Gate Oxide ◽  
Voltage Instability

Threshold-voltage instability in 4H-SiC MOSFETs with nitrided gate oxide revealed by non-relaxation method

2016 ◽  
Vol 55 (4S) ◽  
pp. 04ER11 ◽  
Author(s):  
Mitsuru Sometani ◽  
Dai Okamoto ◽  
Shinsuke Harada ◽  
Hitoshi Ishimori ◽  
Shinji Takasu ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Relaxation Method ◽  
Gate Oxide ◽  
Voltage Instability
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