The Effect of Multiple Interfaces on the Electrical Properties of MgO/Al2O3 Multilayer Gate Stacks on Si Grown by MBE

2014 ◽  
Vol 1691 ◽  
Author(s):  
Chen-Yi Su ◽  
Mariela Menghini ◽  
Jin Won Seo ◽  
Jean-Pierre Locquet
Keyword(s):  
Electrical Properties ◽  
Gate Dielectric ◽  
Frequency Dispersion ◽  
Bottom Layer ◽  
Interface State ◽  
State Density ◽  
Gate Stacks ◽  
Metal Gate ◽  
Multiple Interfaces ◽  
Flatband Voltage

ABSTRACTHigh-κ and metal gate structures have been used to improve the performance of CMOS devices. By changing the materials and structures of the gate dielectric stacks, the flatband voltage (VFB) and the leakage can be changed. We used bilayers and multilayer structures composed of MgO and Al2O3 to verify their influence on the overall electrical properties. Films with an MgO bottom layer generally are found with less flatband voltage shift and lower leakage than with an Al2O3 bottom layer. Also, the frequency dispersion and the interface state density (Dit) are higher for those with MgO bottom layers. MgO films thicker than 0.5 nm effectively shields the positive charges present in the Al2O3.

Properties of Thin SiO2 Films with In-Situ Deposition of Poly Si Electrodes

1989 ◽  
Vol 146 ◽  
Author(s):  
Paihung Pan ◽  
Ahmad Kermani ◽  
Wayne Berry ◽  
Jimmy Liao
Keyword(s):  
Electrical Properties ◽  
Breakdown Strength ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
In Situ Deposition ◽  
Different Temperatures ◽  
Flatband Voltage ◽  
Si Films

ABSTRACTElectrical properties of thin (12 nm) SiO2 films with and without in-situ deposited poly Si electrodes have been studied. Thin SiO2 films were grown by the rapid thermal oxidation (RTO) process and the poly Si films were deposited by the rapid thermal chemical vapor deposition (RTCVD) technique at 675°C and 800°C. Good electrical properties were observed for SiO2 films with thin in-situ poly Si deposition; the flatband voltage was ∼ -0.86 V, the interface state density was < 2 × 1010/cm2/eV, and breakdown strength was > 10 MV/cm. The properties of RTCVD poly Si were also studied. The grain size was 10-60 rim before anneal and was 50-120 rim after anneal. Voids were found in thin (< 70 nm) RTCVD poly Si films. No difference in either SiO2 properties or poly Si properties was observed for poly Si films deposited at different temperatures.

scholarly journals Demonstration of AlGaN/GaN MISHEMT on Si with Low-Temperature Epitaxy Grown AlN Dielectric Gate

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1858
Author(s):  
Matthew Whiteside ◽  
Subramaniam Arulkumaran ◽  
Yilmaz Dikme ◽  
Abhinay Sandupatla ◽  
Geok Ing Ng
Keyword(s):  
Low Temperature ◽  
Gate Dielectric ◽  
Drain Current ◽  
High Electron Mobility Transistors ◽  
Interface State ◽  
State Density ◽  
High Electron ◽  
Gate Leakage ◽  
Annealing Effects ◽  
Low Temperature Epitaxy

AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMT) with a low-temperature epitaxy (LTE)-grown single crystalline AlN gate dielectric were demonstrated for the first time and the post-gate annealing effects at 400 °C were studied. The as-deposited LTE-AlN MISHEMT showed a maximum drain current (IDmax) of 708 mA/mm at a gate bias of 4 V and a maximum extrinsic transconductance (gmmax) of 129 mS/mm. The 400 °C annealed MISHEMT exhibited an increase of 15% in gmmax, an order of magnitude reduction in reverse gate leakage and about a 3% suppression of drain current (ID) collapse. The increase of gmmax by post-gate annealing is consistent with the increase of 2DEG mobility. The suppression of ID collapse and the reduction of gate leakage current is attributed to the reduction of interface state density (5.0 × 1011 cm−2eV−1) between the AlN/GaN interface after post-gate annealing at 400 °C. This study demonstrates that LTE grown AlN is a promising alternate material as gate dielectric for GaN-based MISHEMT application.

Impact of byproducts formed on a 4H–SiC surface on interface state density of Al2O3/4H–SiC(0001) gate stacks

2020 ◽  
Vol 116 (22) ◽  
pp. 222104
Author(s):  
Takuma Doi ◽  
Shigehisa Shibayama ◽  
Wakana Takeuchi ◽  
Mitsuo Sakashita ◽  
Noriyuki Taoka ◽  
...  
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Gate Stacks

Impact of Interfacial Nitridation of HfO2 High-k Gate Dielectric Stack on 4H-SiC

2007 ◽  
Vol 996 ◽  
Author(s):  
Rajat Mahapatra ◽  
Amit K. Chakraborty ◽  
Peter Tappin ◽  
Bing Miao ◽  
Alton B. Horsfall ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Gate Dielectric ◽  
Interface State ◽  
State Density ◽  
Breakdown Field ◽  
Electrical Measurements ◽  
Electrical Stress ◽  
High K ◽  
Pile Up ◽  
Current Characteristics

AbstractHfO2 films were grown on SiO2/4H-SiC and SiON/4H-SiC layers by evaporation of metallic Hf in an electron beam deposition system followed by thermal oxidation. X-ray photoelectron spectroscopy confirmed the formation of HfO2 films. There is no evidence of formation of hafnium silicide or carbon pile up at the surface as well as at the interfacial layer. Electrical measurements show the presence of fewer slow traps in the HfO2/SiON gate dielectric stack on 4H-SiC and comparable values of interface state density. The HfO2/SiON stack layer improves leakage current characteristics with a higher breakdown field and has better reliability under electrical stress.

Passivation and interface state density of SiO2/HfO2-based/polycrystalline-Si gate stacks

2003 ◽  
Vol 83 (3) ◽  
pp. 533-535 ◽  
Author(s):  
R. J. Carter ◽  
E. Cartier ◽  
A. Kerber ◽  
L. Pantisano ◽  
T. Schram ◽  
...  
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Gate Stacks

Processing and Characterization of MOS Capacitors Fabricated on 2°-Off Axis 4H-SiC Epilayers

2016 ◽  
Vol 858 ◽  
pp. 663-666
Author(s):  
Marilena Vivona ◽  
Patrick Fiorenza ◽  
Tomasz Sledziewski ◽  
Alexandra Gkanatsiou ◽  
Michael Krieger ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Interface State ◽  
State Density ◽  
Metal Oxide Semiconductor ◽  
Interface State Density ◽  
Device Fabrication ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Oxide Breakdown

In this work, the electrical properties of SiO2/SiC interfaces onto a 2°-off axis 4H-SiC layer were studied and validated through the processing and characterization of metal-oxide-semiconductor (MOS) capacitors. The electrical analyses on the MOS capacitors gave an interface state density in the low 1×1012 eV-1cm-2 range, which results comparable to the standard 4°-off-axis 4H-SiC, currently used for device fabrication. From Fowler-Nordheim analysis and breakdown measurements, a barrier height of 2.9 eV and an oxide breakdown of 10.3 MV/cm were determined. The results demonstrate the maturity of the 2°-off axis material and pave the way for the fabrication of 4H-SiC MOSFET devices on this misorientation angle.

Structure and Surface Morphology of Thermal SiO2 Grown on 4H-SiC by Metal-Enhanced Oxidation Using Barium

2017 ◽  
Vol 897 ◽  
pp. 340-343 ◽  
Author(s):  
Atthawut Chanthaphan ◽  
Yoshihito Katsu ◽  
Takuji Hosoi ◽  
Takayoshi Shimura ◽  
Heiji Watanabe
Keyword(s):  
Electrical Properties ◽  
Surface Morphology ◽  
Silicon Dioxide ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Surface Roughening ◽  
Oxide Surface ◽  
Capping Layer ◽  
Enhanced Oxidation

Surface morphology and electrical properties of silicon dioxide (SiO2) on 4H-SiC substrates formed by metal-enhanced oxidation (MEO) using barium (Ba) atoms were systematically investigated. It was found that severe surface roughening caused by Ba-MEO can be suppressed by using SiO2 capping prior to MEO. The Ba atoms at the SiO2/SiC interface were found to diffuse to the oxide surface through the deposited SiO2 capping layer, and then the Ba density reduced to ~1014 cm-2 before stable MEO. The resulting SiO2/SiC interface showed the reduced interface state density but the insulating property of the oxides was significantly degraded.

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