All-Semiconducting Nanotube Networks: Towards High Performance Printed Nanoelectronics

2011 ◽  
Vol 1283 ◽  
Author(s):  
N. Rouhi ◽  
D. Jain ◽  
K. Zand ◽  
P. J. Burke

ABSTRACTIn this work, we present progress towards devices fabrication using all semiconducting nanotubes as the starting material. Individual nanotubes are known to have intrinsic mobility of more than 10,000 cm2/V-s but using a network of nanotubes will decrease this mobility because of tube-tube screening effect and junction resistance. Here we are using solution-based deposition of purified 99% semiconducting single-walled nanotubes as the channel in field effect transistors. DC analysis of devices’ characterization shows a high mobility, more than 50 cm2/Vs, and good on/off ratio in the range of more than 103 and 104. A critical issue is the ink formulation and dependence of electronic properties on the nanotube density after deposition. In addition, the channel length also plays an important role in controlling both mobility and on/off ratio.

2015 ◽  
Vol 51 (33) ◽  
pp. 7156-7159 ◽  
Author(s):  
Xuejun Zhan ◽  
Ji Zhang ◽  
Sheng Tang ◽  
Yuxuan Lin ◽  
Min Zhao ◽  
...  

Pyrene fused PDI derivatives are unprecedentedly designed, with the bilateral one possessing a high mobility up to 1.13 cm2 V−1 s−1.


2018 ◽  
Vol 9 (1) ◽  
pp. 2 ◽  
Author(s):  
Sooji Nam ◽  
Yong Jeong ◽  
Joo Kim ◽  
Hansol Yang ◽  
Jaeyoung Jang

Here, we report on the use of a graphene oxide (GO)/polystyrene (PS) bilayer as a gate dielectric for low-voltage organic field-effect transistors (OFETs). The hydrophilic functional groups of GO cause surface trapping and high gate leakage, which can be overcome by introducing a layer of PS—a hydrophobic polymer—onto the top surface of GO. The GO/PS gate dielectric shows reduced surface roughness and gate leakage while maintaining a high capacitance of 37.8 nF cm−2. The resulting OFETs show high-performance operation with a high mobility of 1.05 cm2 V−1 s−1 within a low operating voltage of −5 V.


2020 ◽  
Vol 2 (4) ◽  
pp. 1465-1472
Author(s):  
Marolop Dapot Krisman Simanullang ◽  
G. Bimananda M. Wisna ◽  
Koichi Usami ◽  
Shunri Oda

Demonstration of high-performance p-channel depletion mode field-effect transistors and conductance quantization of multi-mode ballistic Ge-core/a-Si shell nanowires.


2015 ◽  
Vol 51 (60) ◽  
pp. 11961-11963 ◽  
Author(s):  
Yingfeng Wang ◽  
Sufen Zou ◽  
Jianhua Gao ◽  
Huarong Zhang ◽  
Guoqiao Lai ◽  
...  

A remarkable high mobility of 17.9 cm2V−1s−1was obtained for single-crystalline OFET based on 2D molecule BTBTTBT microribbons.


2020 ◽  
Vol 6 (15) ◽  
pp. eaaz4948 ◽  
Author(s):  
Satyaprasad P. Senanayak ◽  
Mojtaba Abdi-Jalebi ◽  
Varun S. Kamboj ◽  
Remington Carey ◽  
Ravichandran Shivanna ◽  
...  

Despite sustained research, application of lead halide perovskites in field-effect transistors (FETs) has substantial concerns in terms of operational instabilities and hysteresis effects which are linked to its ionic nature. Here, we investigate the mechanism behind these instabilities and demonstrate an effective route to suppress them to realize high-performance perovskite FETs with low hysteresis, high threshold voltage stability (ΔVt < 2 V over 10 hours of continuous operation), and high mobility values >1 cm2/V·s at room temperature. We show that multiple cation incorporation using strain-relieving cations like Cs and cations such as Rb, which act as passivation/crystallization modifying agents, is an effective strategy for reducing vacancy concentration and ion migration in perovskite FETs. Furthermore, we demonstrate that treatment of perovskite films with positive azeotrope solvents that act as Lewis bases (acids) enables a further reduction in defect density and substantial improvement in performance and stability of n-type (p-type) perovskite devices.


2012 ◽  
Vol 45 (22) ◽  
pp. 9029-9037 ◽  
Author(s):  
Selvam Subramaniyan ◽  
Felix Sunjoo Kim ◽  
Guoqiang Ren ◽  
Haiyan Li ◽  
Samson A. Jenekhe

Nanophotonics ◽  
2020 ◽  
Vol 9 (16) ◽  
pp. 4719-4728
Author(s):  
Tao Deng ◽  
Shasha Li ◽  
Yuning Li ◽  
Yang Zhang ◽  
Jingye Sun ◽  
...  

AbstractThe molybdenum disulfide (MoS2)-based photodetectors are facing two challenges: the insensitivity to polarized light and the low photoresponsivity. Herein, three-dimensional (3D) field-effect transistors (FETs) based on monolayer MoS2 were fabricated by applying a self–rolled-up technique. The unique microtubular structure makes 3D MoS2 FETs become polarization sensitive. Moreover, the microtubular structure not only offers a natural resonant microcavity to enhance the optical field inside but also increases the light-MoS2 interaction area, resulting in a higher photoresponsivity. Photoresponsivities as high as 23.8 and 2.9 A/W at 395 and 660 nm, respectively, and a comparable polarization ratio of 1.64 were obtained. The fabrication technique of the 3D MoS2 FET could be transferred to other two-dimensional materials, which is very promising for high-performance polarization-sensitive optical and optoelectronic applications.


2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.


2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.


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