High Gain, Silicon-on-insulator Photodetector with Multiple Gates and a Nanowire Based Narrow-wide-narrow Channel

2011 ◽  
Vol 1305 ◽  
Author(s):  
Anita Fadavi Roudsari ◽  
Simarjeet S. Saini ◽  
Nixon O ◽  
M. P. Anantram
Keyword(s):  
Silicon Nanowires ◽  
Narrow Channel ◽  
High Gain ◽  
Silicon On Insulator ◽  
Photo Response ◽  
Charge Flow

ABSTRACTWe propose a phototransistor geometry that incorporates silicon nanowires (SiNW) in the device channel. A set of two gates controls the charge flow inside the NW. This improves the device photo-response more than 10x when compared with a single gate phototransistor, leading to a photo-responsivity of greater than 104(A/W), while the dark properties of both devices are similar.

Nano-Imprint Patterning of Nanowire Structures for Interconnect Study

2005 ◽  
Author(s):  
Bin Li ◽  
Anastassios Mavrokefalos ◽  
Jianhua Zhou ◽  
Li Shi ◽  
Paul S. Ho ◽  
...  
Keyword(s):  
Electron Beam ◽  
Cross Section ◽  
Silicon Nanowires ◽  
Size Effects ◽  
Silicon On Insulator ◽  
Si Nanowires ◽  
Section Surface ◽  
Etching Mask ◽  
Interconnect Lines ◽  
Nano Imprint

A thermal nano-imprint method has been developed to pattern sub-40 nm polymer lines of Hydrogensilsesquioxane (HSQ) and electron beam resist ZEP 520A. The imprint template was the cross section surface of a selectively etched GaAs/AlGaAs heterostructure wafer. Silicon nanowires were formed using reactive ion etching (RIE) of a silicon-on-insulator wafer with the polymer nanolines as an etching mask. The obtained Si nanowires were well defined and continuous for a length up to hundreds of microns. Reaction of the silicon lines with a metal can lead to the formation of silicide interconnect lines, which is used to investigate the size effects on the transport and electromigration properties of interconnects for future microelectronics.

Formation of Single Tiers of Bridging Silicon Nanowires for Transistor Applications Using Vapor-Liquid-Solid Growth from Short Silicon-on-Insulator Sidewalls

Small ◽  
2009 ◽  
Vol 5 (21) ◽  
pp. 2440-2444 ◽  
Author(s):  
Osama M. Nayfeh ◽  
Dimitri A. Antoniadis ◽  
Steven Boles ◽  
Charles Ho ◽  
Carl V. Thompson
Keyword(s):  
Silicon Nanowires ◽  
Silicon On Insulator ◽  
Vapor Liquid Solid ◽  
Vapor Liquid Solid Growth ◽  
Vapor Liquid

Fabrication of SiNWs-FET Nanostructure Via Atomic Force Microscopy Lithography

2020 ◽  
Vol 301 ◽  
pp. 103-110
Author(s):  
Nurain Najihah Alias ◽  
Khatijah Aisha Yaacob ◽  
Kuan Yew Cheong
Keyword(s):  
Atomic Force Microscopy ◽  
Relative Humidity ◽  
Silicon Nanowires ◽  
Silicon Oxide ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Force Microscopy ◽  
Atomic Force ◽  
Effect Transistor ◽  
P Type

The unique electrical properties of silicon nanowires (SiNWs) is one of the reasons it become an attractive transducer for biosensor nowadays. Positive (holes) and negative (electron) charge carriers from SiNWs can simply interact with either positive or negative charge of sensing target. In this paper, we have studied the fabrication of silicon nanowires field effect transistor (SiNWs-FET) nanostructure patterned on 15 Ω resistivity of p-type silicon on insulator (SOI) wafer fabricated via atomic force microscopy lithography technique. To fabricate SiNWs-FET nanostructure, a conductive AFM tip, Cr/Pt cantilever tip, was used then various value of applied voltage, writing speed and relative humidity were studied. Subsequent, followed by wet etching processes, admixture of tetramethylammonium hydroxide (TMAH) and isopropyl alcohol (IPA) were used to remove the undesired of silicon layer and diluted hydrofluoric acid (HF) was used to remove the oxide layer. From the results, it shows that, cantilever tip at 9 V with 0.4 μm/s writing speed and relative humidity between 55% - 60% gives the best formation of silicon oxide to fabricate SiNWs-FET nanostructure.

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