Charge transport in ambipolar pentacene thin film transistors

2011 ◽  
Vol 1286 ◽  
Author(s):  
Ronak Rahimi ◽  
D. Korakakis

ABSTRACTAmbipolar organic transistors are technologically interesting because of their potential applications in light-emitting field-effect transistors [1] and complementary-metal-oxide-semiconductor (CMOS) devices by providing ease of design, low cost of fabrication, and flexibility [2]. Although common organic semiconductors show either n- or p-type charge transport characteristic, organic transistors with ambipolar characteristics have been reported recently. In this work, we show that ambipolar transport can be achieved within a single transistor channel using LiF gate dielectric in the transistors with pentacene active layer. This ambipolar behavior can be controlled by the applied source-drain and gate biases. It was found that at low source-drain biases multistep hopping is the dominant conduction mechanism, while in high voltage regimes I-V data fits in Fowler-Nordheim (F-N) tunneling model. From the slope of the F-N plots, the dependency between field enhancement factor and the transition point in conduction mechanism upon gate bias has been extracted. The transition points show more dependency on gate voltage for negative biases compared to the positive biases. While sweeping negative gate voltages from -5 to -20 V, the source-drain voltages change from about 27 to 17 V. On the other hand, for positive gate voltages from 5 to 20 V, the value of the transition point stays at approximately 36 V. In order to further understand the transport mechanisms, new structures with an interface layer between dielectric and active layer have been fabricated and characterized. As expected, a significant decrease in the amount of the source-drain current has been observed after introducing the interface layer.

2006 ◽  
Vol 913 ◽  
Author(s):  
Joachim Knoch ◽  
Min Zhang ◽  
Qing-Tai Zhao ◽  
Siegfried Mantl

AbstractIn this paper we demonstrate the use of dopant segregation during silicidation for decreasing the effective potential barrier height in Schottky-barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs). N-type as well as p-type devices are fabricated with arsenic/boron implanted into the device's source and drain regions prior to silicidation. During full nickel silicidation a highly doped interface layer is created due to dopants segregating at the silicide-silicon interface. This doped layer leads to an increased tunneling probability through the Schottky barrier and hence leads to significantly improved device characteristics. In addition, we show with simulations that employing ultrathin body (UTB) silicon-on-insulator and ultrathin gate oxides allows to further improve the device characteristics.


Author(s):  
Zheng Zhou ◽  
Jiawei Wang ◽  
Jiezhi Chen ◽  
Chao Jiang ◽  
Ling Li ◽  
...  

We report the charge transport in pentacene polycrystalline organic thin film transistors (OTFTs) with different active layer thicknesses, ranging from a sub-monolayer, bilayer, to tens of nanometers by employing a novel electrode-contact architecture.


2017 ◽  
Vol 5 (24) ◽  
pp. 5872-5876 ◽  
Author(s):  
Tatsuya Mori ◽  
Tatsuya Oyama ◽  
Hideaki Komiyama ◽  
Takuma Yasuda

Strategically dialkylated bis(benzo[4,5]thieno)[2,3-b:3′,2′-d]thiophene molecules having an overall U-shaped configuration can self-organize into bilayer lamellar structures, demonstrating high charge-transport properties in thin-film organic transistors.


2011 ◽  
Vol 1360 ◽  
Author(s):  
Takashi Kushida ◽  
Takashi Nagase ◽  
Hiroyoshi Naito

ABSTRACTAir-mediated molecular ordering in self-organized polymer semiconductors of regioregular poly(3-hexylthiophene) (P3HT) and poly[(9,9′-dioctylfluorenyl-2,7-diyl)-(2,2′-bithiophene-5,5′-diyl)] (F8T2) was investigated using organic field-effect transistors (OFETs) fabricated by transfer-printing using poly(dimethylsiloxane) stamps with various surface energies. OFET measurements revealed that the charge transport in the polymer semiconductors via the air interface layer was better than that via the substrate interface layer. The results indicated that the formation of a highly ordered microstructure at the polymer/air interface through air-mediated self-organization occurs in many polymer semiconductors. This air-mediated self-organization was weaker than substrate-mediated self-organization, whose influence appeared in OFETs with thin semiconductor films.


2003 ◽  
Vol 769 ◽  
Author(s):  
R. Parashkov ◽  
E. Becker ◽  
G. Ginev ◽  
D. Schneider ◽  
D. Metzdorf ◽  
...  

AbstractIn this work we present fully patterned organic transistors based on selective electropolymerization of conducting polymers that enables simple fabrication of micron scale features. It involves fabrication of pentacene field effect transistors in which the conducting, insulating parts as well as the substrate are all made of polymers. We have fabricated drain and source electrodes by electropolymerization of 3,4- ethylenedioxythiophene and gate by spin coating of commercially available poly( 3,4- ethylenedioxythiophene) (PEDOT:PSS) aqueous dispersion, polyvinylalcohol for the gate dielectric layer, and pentacene for the organic active layer. We have built a top-gate structure with gate dielectric layer and gate placed on the top of the pentacene layer, and in a such way obtained protection of the active layer could permit enhancement of the operating time of devices. Carrier mobility as large as 0,01 cm2/V s was measured. Functional all- organic transistors have been realised using a simple and potentially inexpensive technology.


Author(s):  
N. David Theodore ◽  
Andre Vantomme ◽  
Peter Crazier

Contact is typically made to source/drain regions of metal-oxide-semiconductor field-effect transistors (MOSFETs) by use of TiSi2 or CoSi2 layers followed by AI(Cu) metal lines. A silicide layer is used to reduce contact resistance. TiSi2 or CoSi2 are chosen for the contact layer because these silicides have low resistivities (~12-15 μΩ-cm for TiSi2 in the C54 phase, and ~10-15 μΩ-cm for CoSi2). CoSi2 has other desirable properties, such as being thermally stable up to >1000°C for surface layers and >1100°C for buried layers, and having a small lattice mismatch with silicon, -1.2% at room temperature. During CoSi2 growth, Co is the diffusing species. Electrode shorts and voids which can arise if Si is the diffusing species are therefore avoided. However, problems can arise due to silicide-Si interface roughness (leading to nonuniformity in film resistance) and thermal instability of the resistance upon further high temperature annealing. These problems can be avoided if the CoSi2 can be grown epitaxially on silicon.


2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.


Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 441
Author(s):  
Marcello Cioni ◽  
Alessandro Bertacchini ◽  
Alessandro Mucci ◽  
Nicolò Zagni ◽  
Giovanni Verzellesi ◽  
...  

In this paper, we investigate the evolution of threshold voltage (VTH) and on-resistance (RON) drifts in the silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) during the switch-mode operation. A novel measurement setup for performing the required on-the-fly characterization is presented and the experimental results, obtained on commercially available TO-247 packaged SiC devices, are reported. Measurements were performed for 1000 s, during which negative VTH shifts (i.e., VTH decrease) and negative RON drifts (i.e., RON decrease) were observed. To better understand the origin of these parameter drifts and their possible correlation, measurements were performed for different (i) gate-driving voltage (VGH) and (ii) off-state drain voltage (VPH). We found that VTH reduction leads to a current increase, thus yielding RON to decrease. This correlation was explained by the RON dependence on the overdrive voltage (VGS–VTH). We also found that gate-related effects dominate the parameter drifts at low VPH with no observable recovery, due to the repeated switching of the gate signal required for the parameter monitoring. Conversely, the drain-induced instabilities caused by high VPH are completely recoverable within 1000 s from the VPH removal. These results show that the measurement setup is able to discern the gate/drain contributions, clarifying the origin of the observed VTH and RON drifts.


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